Patents by Inventor Steven Alan Lytle
Steven Alan Lytle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10665596Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.Type: GrantFiled: October 23, 2018Date of Patent: May 26, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Steven Alan Lytle
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Publication number: 20190057969Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.Type: ApplicationFiled: October 23, 2018Publication date: February 21, 2019Inventor: Steven Alan LYTLE
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Patent number: 10134746Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.Type: GrantFiled: March 23, 2017Date of Patent: November 20, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Steven Alan Lytle
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Publication number: 20170194332Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.Type: ApplicationFiled: March 23, 2017Publication date: July 6, 2017Inventor: Steven Alan LYTLE
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Patent number: 9640539Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.Type: GrantFiled: December 16, 2015Date of Patent: May 2, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Steven Alan Lytle
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Publication number: 20160104710Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.Type: ApplicationFiled: December 16, 2015Publication date: April 14, 2016Inventor: Steven Alan LYTLE
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Patent number: 9245894Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.Type: GrantFiled: December 8, 2014Date of Patent: January 26, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Steven Alan Lytle
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Publication number: 20150171091Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.Type: ApplicationFiled: December 8, 2014Publication date: June 18, 2015Inventor: Steven Alan LYTLE
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Patent number: 8728945Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.Type: GrantFiled: November 3, 2011Date of Patent: May 20, 2014Assignee: Texas Instruments IncorporatedInventor: Steven Alan Lytle
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Publication number: 20120108068Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.Type: ApplicationFiled: November 3, 2011Publication date: May 3, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Steven Alan Lytle
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Patent number: 7160799Abstract: The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.Type: GrantFiled: June 24, 2003Date of Patent: January 9, 2007Assignee: Agere Systems Inc.Inventors: Steven Alan Lytle, Thomas Michael Wolf, Allen Yen
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Patent number: 6879046Abstract: A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N—H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide.Type: GrantFiled: January 2, 2002Date of Patent: April 12, 2005Assignee: Agere Systems Inc.Inventors: Gerald W Gibson, Jr., Scott Jessen, Steven Alan Lytle, Kurt George Steiner, Susan Clay Vitkavage
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Publication number: 20030003765Abstract: A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N—H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide.Type: ApplicationFiled: January 2, 2002Publication date: January 2, 2003Inventors: Gerald W. Gibson, Scott Jessen, Steven Alan Lytle, Kurt George Steiner, Susan Clay Vitkavage
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Patent number: 6362638Abstract: A method and apparatus for measuring Kelvin contact resistance within an integrated circuit interconnect is provided, having upper and lower Kelvin contact resistance contacts covering a via and interconnect being measured, along with a third conductor placed substantially between the upper and lower Kelvin contacts, and in contact with the via.Type: GrantFiled: September 1, 1999Date of Patent: March 26, 2002Assignee: Agere Systems Guardian Corp.Inventors: Robert Alan Ashton, Steven Alan Lytle, Mary Drummond Roby, Daniel Joseph Vitkavage
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Patent number: 6329281Abstract: The present invention utilizes a selective overlayer to provide more efficient fabrication of a dual damascene multilevel interconnect structure. The selective overlayer serves as a protective mask which prevents the upper layer of the composite layer from being eroded during the formation of the multi-level interconnects. The present invention also solves some of the problems associated with the full-via first and partial-via first fabrication methods because the selective overlayer enables an efficient, deep partial via to be formed while preventing the deposit of undeveloped photoresist in subsequent fabrication steps. The present invention also provides advantages during the planarization and polishing of the dual damascene structure after the deposition of the conductive layer because the selective overlayer allows for efficient planarization without loss of trench depth control.Type: GrantFiled: December 3, 1999Date of Patent: December 11, 2001Assignee: Agere Systems Guardian Corp.Inventors: Steven Alan Lytle, Mary Drummond Roby, Daniel Joseph Vitkavage
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Patent number: 5891784Abstract: A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. An anti-reflective coating helps protect against reflective gate notching. A variety of silicided and non-silicided) structures may be formed.Type: GrantFiled: April 27, 1995Date of Patent: April 6, 1999Assignee: Lucent Technologies, Inc.Inventors: Wan Yee Cheung, Sailesh Chittipeddi, Chong-Cheng Fu, Taeho Kook, Avinoam Kornblit, Steven Alan Lytle, Kurt George Steiner, Tungsheng Yang
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Patent number: 5712176Abstract: A process for forming a P.sub.2 O.sub.5 layer suitable for diffusion doping polysilicon gates is disclosed. The inventive process has a reduced thermal budget and helps to eliminate subsequent gate oxide roughness.Type: GrantFiled: June 30, 1995Date of Patent: January 27, 1998Assignee: Lucent Technologies Inc.Inventors: Steven Alan Lytle, Yaw Samuel Obeng, Eric John Persson