Abstract: A decoding circuit, is provided, comprising: a turbo decoder configured to receive a input systematic bit soft information values and input parity bit information values, and to generate output systematic bit soft information values and hard decoded bits according to a turbo decoding operation; and a parity bit soft information generation circuit configured to receive the input systematic bit soft information values, the input parity bit soft information values, and the output systematic bit soft information values; to determine initial forward metrics, initial backward metrics, and branch metrics as a function of the input parity bit soft information values and the output systematic bit soft information values; to determine output parity bit soft information values based on the branch metrics, the initial forward metrics, and the initial backward metrics; and to provide the output parity bit soft information values as a signal output.

Abstract: A decoding circuit, is provided, comprising: a turbo decoder configured to receive a input systematic bit soft information values and input parity bit information values, and to generate output systematic bit soft information values and hard decoded bits according to a turbo decoding operation; and a parity bit soft information generation circuit configured to receive the input systematic bit soft information values, the input parity bit soft information values, and the output systematic bit soft information values; to determine initial forward metrics, initial backward metrics, and branch metrics as a function of the input parity bit soft information values and the output systematic bit soft information values; to determine output parity bit soft information values based on the branch metrics, the initial forward metrics, and the initial backward metrics; and to provide the output parity bit soft information values as a signal output.

Abstract: A system is provided for correcting phase jitter and frequency offsets in QAM modems. The system comprises (i) a narrow bandwidth, decision directed, phase-locked loop for tracking the average phase and frequency offsets followed by (ii) a phase jitter corrector located outside of the loop. The phase error signal for the jitter corrector is produced by passing the phase error signal of the phase-locked loop through a low pass filter designed to pass the expected jitter frequencies. Inphase and quadrature signals from the loop are delayed to compensate for the delay of the low pass filter, and the delayed signals, together with the filter output, are applied to a phase shifter which provides phase jitter correction using a rotational transformation.