Abstract: Multi-stage switching networks may be constructed and expanded from small to very large networks that are contained within a compact physical volume. This is accomplished by replication of a pre-selected network module containing switches by a rotating, folding and squaring process that substantially reduces the length of connections between switches. This geometry allows very large networks by inductively combining smaller networks into larger networks. In networks constructed with this geometry, the length of the longest connections between switches is proportional to the square root of the number of ports provided by the network.

Abstract: An expandable network constructed from a plurality of identical network fabric cards which uses a plurality of selected row address bits to route connection paths between adjacent columns of interconnecting switches and a software algorithm for implementing a network of any whole number power of 2 rows or ports by assigning numbers of the network switches and attached nodes are described.

Abstract: The Scalable Coherent Interface (SCI) standard of the Institute of Electrical and Electronics Engineers is intended for fast, high throughput, point-to-point, unidirectional links. It is to serve high-performance multiprocessor systems. A number of key elements are defined as part of the protocol for SCI. These include: (a) command.old which is a bit in transmitted packets for detecting stale packets to discard; (b) idle.cc which is an idle bit to be inserted between packets for detecting lost packets which toggles when the idle bit has circulated around the ringlet; and (c) idle.ac which is an idle bit which toggles when all operational nodes have had an opportunity to transmit. In addition, SCI contemplates the implementation of a number of different types of resets, including power reset, upon read or apparent loss of power for more than a second and linc reset for clearing circuits but not changing error count registers in the system.

Abstract: The Scalable Coherent Interface (SCI) standard of the Institute of Electrical and Electronics Engineers is intended for fast, high throughput, point-to-point, unidirectional links to high-performance multiprocessor systems. A system is provided for routing packets with a plurality of data bits and target identity code bits through a packet routing switching network. The packets are transmitted from source nodes through the switching network to target nodes that are designated by the target identity code bits. Operational rings are used to link output ports of switches of the output stages to input ports of switches of the input stage wherein each operational ring is identified by ring identity code bits associated with the input stage switches of the operational rings and has at least one node which is capable of performing a function with the data. Recirculation rings are used to link output ports of switches of the output stage to input ports of switches of the input stage.

Abstract: A multi-node Scalable Coherent Interface ring for the transmission of packets between nodes, each of which contains an SCI link controller to which a B-link controller that contains a timer is coupled and a gigabit transceiver to which a G-link controller that contains a timer is coupled, is provided. The SCI link controller, the B-link controller and the G-link controller are utilized to allow the SCI link controller and the transceivers to be initialized and synchronized in a manner such that these devices may be utilized in a multi-node SCI packet network.

Abstract: The Scalable Coherent Interface (SCI) standard of the Institute of Electrical and Electronics Engineers is intended for fast, high throughput, unidirectional links to high-performance multiprocessor systems. Key elements of the protocol for SCI include: (a) a "new/stale" bit which is generated in a data packet for detecting stale packets to discard; (b) an idle.cc which is an idle bit to be inserted between packets for detecting lost packets which toggles when the idle bit has circulated around the ringlet; and (c) a scrubber node in each operational ring of an SCI network which toggles "new/stale" bits from a "new" state to a stale state when they are received at the scrubber node. The "new/stale" bit is also set to a "new" stale bit when a packet is generated in a source node in a first operational ring for transmission to a target node in a second operational ring. A scrubber node is located as the first node of each operational ring of the network. The new/stale" bit and the idle circulation (idle.

Abstract: A deadlock avoidance system for avoiding interconnection deadlocks between a plurality of data transfer devices includes a controller, a switch interconnector coupled to all of said data transfer devices for interconnecting on a one-to-one basis selected ones of the data transfer device as requesting units to selected ones of said data transfer devices as receiving units. A transfer queue is employed that includes a master transfer register and a slave transfer register, a master register, a slave register and a target register.