Abstract: A measuring apparatus including a self test function, the circuit comprising a capacitor; first to fourth switches; a test signal injector; at least one comparator having a signal input and a reference input the first switch being interposed between a first plate of the capacitor and a first input node, the second switch being interposed between a second plate of the capacitor and a second input node, the third switch being interposed between the first plate of the capacitor and the signal input of the comparator and the fourth switch being interposed between the second plate of the capacitor and a voltage reference, wherein the self test function comprises the steps of i) operating the signal injector to produce a first signal representative of an out of range voltage for an expected voltage difference between the first and second input nodes, and using the signal to cause the at least one comparator to place its output in an error state, and to charge the capacitor to the out of range voltage, ii) isolating

Abstract: A measuring apparatus including a self test function, the circuit comprising a capacitor; first to fourth switches; a test signal injector; at least one comparator having a signal input and a reference input the first switch being interposed between a first plate of the capacitor and a first input node, the second switch being interposed between a second plate of the capacitor and a second input node, the third switch being interposed between the first plate of the capacitor and the signal input of the comparator and the fourth switch being interposed between the second plate of the capacitor and a voltage reference, wherein the self test function comprises the steps of i) operating the signal injector to produce a first signal representative of an out of range voltage for an expected voltage difference between the first and second input nodes, and using the signal to cause the at least one comparator to place its output in an error state, and to charge the capacitor to the out of range voltage, ii) isolating

Abstract: A high-bandwidth direct communication path between two clients is used for voice or video calls over the Internet. An opening or a window in a firewall is made for the direct path by sending a null packet out from inside the firewall. The null packet can be a UDP packet directed to a UDP port of the other client. Initially, each client makes a TCP connection to port 80 of an external manager. Each client registers its UDP port number with the external manager. A call request from one client to the external manager results in a message from the external manager to the other client. The other client then creates the window in its firewall by transmitting the null UDP packet. Then the external manager is notified and tells the calling client to begin sending UDP packets directly to the other client through the firewall window.

Abstract: An integrated circuit package comprising EMI containment features. The EMI containment features include a first EMI containment configuration and a second EMI containment configuration. The second EMI containment configuration is disposed around the first EMI containment configuration. The first and second EMI containment configurations include vias coupled to at least one ground plane of the integrated circuit package.

Abstract: A method and system providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expos at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

Abstract: A method for providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expose at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.