Patents by Inventor Steven C. Barner
Steven C. Barner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210081572Abstract: An encryption interface provides secure, low-latency communications between processors. A first processor block transforms initial data into encrypted data using a cipher for receipt by a second processor block, which transforms the encrypted data into decrypted data. The first processor block utilized a crypto circuit having a plurality of stages, each of which generate a subset of a cipher digit stream for encrypting the data. The second processor block receives and decrypts the encrypted data using a respective decryption circuit.Type: ApplicationFiled: November 13, 2020Publication date: March 18, 2021Inventors: Georgios Angelopoulos, Steven C. Barner, Richard E. Kessler
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Patent number: 10872173Abstract: An encryption interface provides secure, low-latency communications between processors. A first processor block transforms initial data into encrypted data using a cipher for receipt by a second processor block, which transforms the encrypted data into decrypted data. The first processor block utilized a crypto circuit having a plurality of stages, each of which generate a subset of a cipher digit stream for encrypting the data. The second processor block receives and decrypts the encrypted data using a respective decryption circuit.Type: GrantFiled: September 26, 2018Date of Patent: December 22, 2020Assignee: Marvell Asia Pte, Ltd.Inventors: Georgios Angelopoulos, Steven C. Barner, Richard E. Kessler
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Publication number: 20200097681Abstract: An encryption interface provides secure, low-latency communications between processors. A first processor block transforms initial data into encrypted data using a cipher for receipt by a second processor block, which transforms the encrypted data into decrypted data. The first processor block utilized a crypto circuit having a plurality of stages, each of which generate a subset of a cipher digit stream for encrypting the data. The second processor block receives and decrypts the encrypted data using a respective decryption circuit.Type: ApplicationFiled: September 26, 2018Publication date: March 26, 2020Inventors: Georgios Angelopoulos, Steven C. Barner, Richard E. Kessler
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Patent number: 10592452Abstract: In one embodiment, a data message is generated at a first system-on-chip (SOC) for transmission to a second SOC. A stream of data words is generated from the data message, the data words alternating between even and odd data words. Each data word in the stream of data words is divided into a first pattern of slices for even data words and a second pattern of slices for odd data words, with the slices distributed across plural output ports at the first SOC. At each output port, two slices from two successive cycles are grouped. The grouped slices are encoded using an encoding scheme to produce an N-bit symbol at M-bits per cycle, alternating between high and low parts of the encoding. Plural metaframes are generated from a stream of symbols and the metaframes for each of the output ports are transmitted to the second SOC.Type: GrantFiled: September 12, 2018Date of Patent: March 17, 2020Assignee: CAVIUM, LLCInventor: Steven C. Barner
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Publication number: 20200081857Abstract: In one embodiment, a data message is generated at a first system-on-chip (SOC) for transmission to a second SOC. A stream of data words is generated from the data message, the data words alternating between even and odd data words. Each data word in the stream of data words is divided into a first pattern of slices for even data words and a second pattern of slices for odd data words, with the slices distributed across plural output ports at the first SOC. At each output port, two slices from two successive cycles are grouped. The grouped slices are encoded using an encoding scheme to produce an N-bit symbol at M-bits per cycle, alternating between high and low parts of the encoding. Plural metaframes are generated from a stream of symbols and the metaframes for each of the output ports are transmitted to the second SOC.Type: ApplicationFiled: September 12, 2018Publication date: March 12, 2020Inventor: Steven C. Barner
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Patent number: 9933809Abstract: Pacing of a producer, operating in a producer clock domain, may be based on at least one heuristic of a credit wire that is used to return credits to the producer. The returned credits may indicate that a consumer, operating in a consumer clock domain, has consumed data produced by the producer. The at least one heuristic may be a rate at which the credits are returned to the producer. Pacing the producer based on the rate at which the credits are returned to the producer may reduce latency of the data, flowing from the producer clock domain to the consumer clock domain, by minimizing an average number of entries in use in a First-In-First-Out (FIFO) operating in a pipeline between the producer and the consumer.Type: GrantFiled: November 13, 2015Date of Patent: April 3, 2018Assignee: Cavium, Inc.Inventor: Steven C. Barner
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Patent number: 9824058Abstract: A group of low-level FIFOs may be logically bound together to form a super-FIFO. The super-FIFO may treat each low-level FIFO as a storage location. The super-FIFO may enable a push to (or a pop from) every low-level FIFO, simultaneously. The super-FIFO may enable a virtual channel (VC) to use the super-FIFO, bypassing a VC FIFO for the VC, removing several cycles of latency otherwise needed for enqueuing and dequeuing messages in the VC FIFO. In addition, the super-FIFO may enable bypassing of an arbiter, further reducing latency by avoiding a penalty of the arbiter.Type: GrantFiled: November 14, 2014Date of Patent: November 21, 2017Assignee: Cavium, Inc.Inventor: Steven C. Barner
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Patent number: 9471416Abstract: A circuit provides parallel computation of error codes for simultaneously received words. The words received simultaneously may be portions of a common data message, or may be portions of distinct data messages. Accordingly, the circuit selectively accumulates the error codes based on their association with successive data words, outputting an accumulated error code when the last word of a data message has been received and the respective error code is calculated. Based on such information, the error codes calculated in parallel can be output independently, accumulated with one another, or accumulated with the error codes of a previous or subsequent calculation cycle. Thus, the circuit dynamically provides a single parallel error code generation of a given width or multiple parallel error code generations, each of a width divisible by the given width.Type: GrantFiled: February 28, 2014Date of Patent: October 18, 2016Assignee: Cavium, Inc.Inventor: Steven C. Barner
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Patent number: 9432288Abstract: A network processing system provides coherent communications between multiple system-on-chips (SOCs). Data messages between SOCs are assigned to virtual channels. An interconnect linking the SOCs divides the communications into discrete data blocks, each of which contains data segments from several virtual channels. The virtual channels can be implemented to control congestion and interference among classes of communications. During transmission, the interconnect distributes the data blocks across several physical ports linking the SOCs. As a result, communications between SOCs is optimized with minimal latency.Type: GrantFiled: February 28, 2014Date of Patent: August 30, 2016Assignee: Cavium, Inc.Inventors: Steven C. Barner, Craig A. Thomas
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Publication number: 20160139880Abstract: A group of low-level FIFOs may be logically bound together to form a super-FIFO. The super-FIFO may treat each low-level FIFO as a storage location. The super-FIFO may enable a push to (or a pop from) every low-level FIFO, simultaneously. The super-FIFO may enable a virtual channel (VC) to use the super-FIFO, bypassing a VC FIFO for the VC, removing several cycles of latency otherwise needed for enqueuing and dequeuing messages in the VC FIFO. In addition, the super-FIFO may enable bypassing of an arbiter, further reducing latency by avoiding a penalty of the arbiter.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventor: Steven C. Barner
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Publication number: 20160139622Abstract: Pacing of a producer, operating in a producer clock domain, may be based on at least one heuristic of a credit wire that is used to return credits to the producer. The returned credits may indicate that a consumer, operating in a consumer clock domain, has consumed data produced by the producer. The at least one heuristic may be a rate at which the credits are returned to the producer. Pacing the producer based on the rate at which the credits are returned to the producer may reduce latency of the data, flowing from the producer clock domain to the consumer clock domain, by minimizing an average number of entries in use in a First-In-First-Out (FIFO) operating in a pipeline between the producer and the consumer.Type: ApplicationFiled: November 13, 2015Publication date: May 19, 2016Inventor: Steven C. Barner
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Publication number: 20150249602Abstract: A network processing system provides coherent communications between multiple system-on-chips (SOCs). Data messages between SOCs are assigned to virtual channels. An interconnect linking the SOCs divides the communications into discrete data blocks, each of which contains data segments from several virtual channels. The virtual channels can be implemented to control congestion and interference among classes of communications. During transmission, the interconnect distributes the data blocks across several physical ports linking the SOCs. As a result, communications between SOCs is optimized with minimal latency.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Applicant: Cavium, Inc.Inventors: Steven C. Barner, Craig A. Thomas
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Publication number: 20150248323Abstract: A circuit provides parallel computation of error codes for simultaneously received words. The words received simultaneously may be portions of a common data message, or may be portions of distinct data messages. Accordingly, the circuit selectively accumulates the error codes based on their association with successive data words, outputting an accumulated error code when the last word of a data message has been received and the respective error code is calculated. Based on such information, the error codes calculated in parallel can be output independently, accumulated with one another, or accumulated with the error codes of a previous or subsequent calculation cycle. Thus, the circuit dynamically provides a single parallel error code generation of a given width or multiple parallel error code generations, each of a width divisible by the given width.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Applicant: Cavium, Inc.Inventor: Steven C. Barner