Abstract: A high speed, compact low power integer adder unit for advanced microprocessors features modular construction, low gate count and a fast add time. A 64-bit implementation is characterized by a unique combination of dual rail logic circuits and dual carry select path within each of four 16-bit adder building blocks to achieve a one gate delay increment for each additional 16-bit adder building block after the first. Each of the 16-bit adder building blocks are composed of modules that receive four of sixteen bits of the operands, and each of the modules are comprised of submodules. The submodules are in turn comprised of dual rail logic circuits with a dual carry select path so as to constitute a nested carry select architecture wherein the nesting of the dual carry select path extends from submodules to a module and from modules to a basic building block.