Abstract: The present invention provides parity error detection circuitry to effect an automatic second transmission of the data information signals in the event that a first transmission of said data information signals is determined to have a parity error. The invention includes a latch register through which data information signals are transmitted from a slave device to a master device and, there is also included parity check circuitry. When a parity error occurs in the transmission of data information signals, a parity error signal is generated by the master device which ultimately causes the latch register to hold the information which was previously transmitted as data signals and which data signals gave rise to the parity error. Accordingly a second set of data signals can be transmitted from the latch register, in an attempt to get a transmission of said data signals without error.

Abstract: The present invention includes a counter device which counts pulses from a pulse source and provides the basis for a control gate signal. Logic circuitry is connected to the counter device and through said logic circuitry there are provided the leading edge, the interim voltage level signal, and the trailing edge of said control gate signal. The counter device is connected from at least two latter stages to said logic circuitry to provide two possible trailing edges, which in turn selectively define two different length gate signals. Said logic circuitry is further connected to address signal circuitry and in response to a first address provides a control gate signal of a first length and in response to a second address provides a control gate signal of a second length.