Abstract: A novel high speed unidirectional bus system is provided for receiving a plurality of novel circuit card assemblies in receptacles on the bus. Adjacent receptacles are connected by lines on the bus which interconnect output pins to input pins. The circuit between output pins and input pins are formed by connecting the plugs on circuit card assemblies into the receptacles on said bus. The system comprises a plurality of function circuit card assemblies connected in a daisy chain when inserted into adjacent receptacles on said bus between a source circuit card assembly and a destination circuit card assembly and the address portion of the information supplied by the source circuit card assembly is programmed to identify the function circuit card assembly to first receive the source data whereby the unidirectional bus system may be operated in a time division random access mode at data rates in excess of the data rates of individual functional circuit card assemblies.

Abstract: A novel interface unit circuit for connecting circuit card assemblies to a data stream and to each other is designed for implementation on a high speed semiconductor chip. A parallel bit data word comprising a programmable address field is compared to a mask address stored in buffer registers and in the presence of a match, the parallel bit data word is stored in a sink register. Also the address field of the data word is filled with zeros and passed to the output of the data channel where the time slot for the data word may be written over with new data words or the time slot passed on to other circuit card assemblies or other elements.

Abstract: An improved interface unit for receiving a stream of parallel bit words from a source bus comprising an address field, a data field and a clock field. The parallel bit words are first phase adjusted and stored in an input register where the address field is compared in enable logic to determine whether to store the data field in a sink buffer register for processing. The word in the input register is coupled to the buffer storage register. The address field is further compared in pass through disable logic to determine whether to pass the address and data field to an output register or to generate a null code address in the address field of the word being outputted from the buffer storage register. The word in the buffer storage register is coupled through a word selector to an output register.