Patents by Inventor Steven C. Woo
Steven C. Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250028636Abstract: Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.Type: ApplicationFiled: August 5, 2024Publication date: January 23, 2025Inventors: Taeksang SONG, Steven C. WOO, Torsten PARTSCH
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Publication number: 20250028467Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also has one or more custom logic, controller, or processor die. The custom die(s) of the stack include direct channel interfaces that allow direct access to memory regions on one or more DRAMs in the stack. The direct channels are time-division multiplexed such that each DRAM die is associated with a time slot on a direct channel. The custom die configures a first DRAM die to read a block of data and transmit it via the direct channel using a time slot that is assigned to a second DRAM die. The custom die also configures the second memory device to receive the first block of data in its assigned time slot and write the block of data.Type: ApplicationFiled: August 5, 2024Publication date: January 23, 2025Inventors: Michael Raymond MILLER, Steven C. Woo, Thomas Vogelsang
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Patent number: 12174749Abstract: The creation, maintenance, and accessing of page tables is done by a virtual machine monitor running on a computing system rather than the guest operating systems. This allows page table walks to be completed in fewer memory accesses when compared to the guest operating system's maintenance of the page tables. In addition, the virtual machine monitor may utilize additional resources to offload page table access and maintenance functions from the CPU to another device, such as a page table management device or page table management node. Offloading some or all page table access and maintenance functions to a specialized device or node enables the CPU to perform other tasks during page table walks and/or other page table maintenance functions.Type: GrantFiled: January 14, 2022Date of Patent: December 24, 2024Assignee: Rambus Inc.Inventors: Steven C. Woo, Christopher Haywood, Evan Lawrence Erickson
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Publication number: 20240394195Abstract: A dynamic random access memory (DRAM) device includes functions configured to aid with operating the DRAM device as part of data caching functions. The DRAM is configured to respond to at least two types of commands. A first type of command (cache data access command) seeks to access a cache line of data, if present in the DRAM cache. A second type of command (cache probe command) seeks to determine whether a cache line of data is present, but is not requesting the data be returned in response. In response to these types of access commands, the DRAM device is configured to receive cache tag query values and to compare stored cache tag values with the cache tag query values. A hit/miss (HM) interface/bus may indicate the result of the cache tag compare and stored cache line status bits to a controller.Type: ApplicationFiled: May 15, 2024Publication date: November 28, 2024Inventors: Steven C. WOO, Michael Raymond MILLER, Taeksang SONG, Wendy ELSASSER, Maryam BABAIE
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Publication number: 20240393982Abstract: A memory module supports multiple memory channel modes, each including a double-date-rate (DDR) data channel supported by an independent command-and-address (CA) channel. In a two-channel mode, the memory module supports two DDR data channels using two respective DDR CA channels. Each CA channel includes a corresponding set of CA links. In a four-channel mode, the memory module supports two pairs of DDR data channels, each pair supported by a pair of independent CA channels. Memory commands issued in the four-channel mode are time interleaved to share one of the sets of CA links.Type: ApplicationFiled: August 5, 2024Publication date: November 28, 2024Inventors: Dongyun Lee, Steven C. Woo
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Publication number: 20240370361Abstract: Multiple (e.g., four) memory devices on a module are connected to a common pair of differential data strobe signal conductors. The common pair of differential data strobe conductors are also coupled to a memory controller to time the transmission of data to the multiple memory devices and to time the reception of data from the memory devices. The controller calibrates two or more different data transmission delays relative to its transmission of a write data strobe signal on the common pair of differential data strobe conductors. The controller also calibrates to account for two or more different data reception delays (skew) relative to its reception of a read data strobe signal on the common pair of differential data strobe conductors.Type: ApplicationFiled: August 23, 2022Publication date: November 7, 2024Inventors: Joohee KIM, Dongyun LEE, Steven C. WOO
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Publication number: 20240370331Abstract: A random access memory device includes memory cells in each row for storing metadata related to accesses to that row. These metadata dedicated memory cells may store counter values that may be updated (e.g., incremented or decremented) when certain events occur (e.g., activate row—ACT, column read—CAS, error detected, etc.). Which events cause an update of the metadata stored in a row, and under what conditions related to the metadata/count value (e.g., threshold, match, threshold value, etc.) cause further action to be taken (e.g., alert controller, set mode register, etc.) are configurable by a controller. Additional functions related to the metadata/counters are also configurable such as scanning counter values to determine the row address with highest or lowest value and pattern matching (e.g., process identification match/mismatch).Type: ApplicationFiled: April 29, 2024Publication date: November 7, 2024Inventors: Taeksang SONG, John Eric LINSTADT, Steven C. WOO, Craig E. HAMPEL, Brent Steven HAUKNESS, Christopher HAYWOOD
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Patent number: 12136452Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: GrantFiled: June 14, 2023Date of Patent: November 5, 2024Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
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Publication number: 20240354014Abstract: A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.Type: ApplicationFiled: May 6, 2024Publication date: October 24, 2024Inventors: Thomas Vogelsang, Steven C. Woo, Michael Raymond Miller
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Patent number: 12125556Abstract: A memory system includes a memory controller, a plurality of serial data buffers, and a plurality of memory devices. The memory controller issues packetized commands and data to the serial data buffers. The serial data buffers each apply a different remapping function to remap an input command address in the packetized commands to respective remapped memory addresses that are different for each serial data buffer. The serial data buffers then issue commands to the memory devices using the remapped addresses. The remapping functions may be designed to mitigate row hammer effects. The serial data buffers may furthermore apply transformations to read and write data to facilitate encryption and decryption.Type: GrantFiled: August 29, 2022Date of Patent: October 22, 2024Assignee: Rambus Inc.Inventors: Christopher Haywood, Steven C. Woo
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Patent number: 12124392Abstract: Multiple device stacks are interconnected in a ring topology. The inter-device stack communication may utilize a handshake protocol. This ring topology may include the host so that the host may initialize and load the device stacks with data and/or commands (e.g., software, algorithms, etc.). The inter-device stack interconnections may also be configured to include/remove the host and/or to implement varying numbers of separate ring topologies. By configuring the system with more than one ring topology, and assigning different problems to different rings, multiple, possibly unrelated, machine learning tasks may be performed in parallel by the device stack system.Type: GrantFiled: August 4, 2023Date of Patent: October 22, 2024Assignee: Rambus Inc.Inventor: Steven C. Woo
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Publication number: 20240311334Abstract: A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.Type: ApplicationFiled: April 2, 2024Publication date: September 19, 2024Inventors: Steven C. Woo, Michael Raymond Miller
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Publication number: 20240311301Abstract: A dynamic random access memory (DRAM) device includes functions configured to aid with operating the DRAM device as part of data caching functions. In response to some write and/or read access commands, the DRAM device is configured to copy a cache line (e.g., dirty cache line) from the main DRAM memory array, place it in a flush buffer, and replace the copied cache line in the main DRAM memory array with a new (e.g., different) cache line of data. In response to conditions and/or events (e.g., explicit command, refresh, write-to-read command sequence, unused data bus bandwidth, full flush buffer, etc.) the DRAM device transmits the cache line from the flush buffer to the controller. The controller may then transmit the cache line to other cache levels.Type: ApplicationFiled: March 7, 2024Publication date: September 19, 2024Inventors: Michael Raymond MILLER, Steven C. Woo, Wendy Elsasser, Taeksang Song
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Patent number: 12086060Abstract: Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.Type: GrantFiled: August 23, 2022Date of Patent: September 10, 2024Assignee: Rambus Inc.Inventors: Taeksang Song, Steven C. Woo, Torsten Partsch
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Patent number: 12086441Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also has one or more custom logic, controller, or processor die. The custom die(s) of the stack include direct channel interfaces that allow direct access to memory regions on one or more DRAMs in the stack. The direct channels are time-division multiplexed such that each DRAM die is associated with a time slot on a direct channel. The custom die configures a first DRAM die to read a block of data and transmit it via the direct channel using a time slot that is assigned to a second DRAM die. The custom die also configures the second memory device to receive the first block of data in its assigned time slot and write the block of data.Type: GrantFiled: August 30, 2021Date of Patent: September 10, 2024Assignee: Rambus Inc.Inventors: Michael Raymond Miller, Steven C. Woo, Thomas Vogelsang
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Publication number: 20240295961Abstract: An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.Type: ApplicationFiled: March 7, 2024Publication date: September 5, 2024Inventors: Michael Raymond Miller, Steven C. Woo, Thomas Vogelsang
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Publication number: 20240272982Abstract: A four-channel memory module includes four independent twenty (20) data bit memory channels and dual channel memory devices. The channels of the dual channel memory are accessed independently. Thus, the four channels for accessing the memory module each access one channel of a first set and a second set of dual channel memory devices on the module. Error detection and correction codeword configurations and schemes can implement chipkill, Single symbol data correct/double symbol data detect (SSDC/DSDD). Single symbol data correct with fewer memory devices may also be implemented. Error detection and correction codeword configurations and schemes may be switched in response to detecting a failed device, signal line, or memory channel.Type: ApplicationFiled: June 21, 2022Publication date: August 15, 2024Inventors: Steven C. WOO, Dongyun LEE
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Publication number: 20240274181Abstract: The internal row addressing of each DRAM on a module is mapped such that row hammer affects different neighboring row addresses in each DRAM. Because the external row address to internal row address mapping scheme ensures that each set of neighboring rows for a given externally addressed row is different for each DRAM on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each DRAM. This has the effect of confining the row hammer errors for each row that is hammered to a single DRAM per externally addressed neighboring row. By confining the row hammer errors to a single DRAM, the row hammer errors are correctible using a single device data correct (SDDC) scheme.Type: ApplicationFiled: February 22, 2024Publication date: August 15, 2024Inventors: Steven C. WOO, Taeksang SONG
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Publication number: 20240241670Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die has a base logic die and one or more custom logic or processor die. The processor logic die snoops commands sent to and through the stack. In particular, the processor logic die may snoop mode setting commands (e.g., mode register set—MRS commands). At least one mode setting command that is ignored by the DRAM in the stack is used to communicate a command to the processor logic die. In response the processor logic die may prevent commands, addresses, and data from reaching the DRAM die(s). This enables the processor logic die to send commands/addresses and communicate data with the DRAM die(s). While being able to send commands/addresses and communicate data with the DRAM die(s), the processor logic die may execute software using the DRAM die(s) for program and/or data storage and retrieval.Type: ApplicationFiled: January 30, 2024Publication date: July 18, 2024Inventors: Thomas VOGELSANG, Michael Raymond MILLER, Steven C. WOO
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Publication number: 20240211420Abstract: A four-channel memory module includes four independent memory channels and dual channel memory devices. The channels of the dual channel memory are accessed independently. Thus, the four channels for accessing the memory module each access one channel of a first set and a second set of dual channel memory devices on the module. Dual channel data buffer devices are also included on the module. The dual channel data buffer devices also retime data strobe signals for accesses to/from the sets of dual channel memory devices.Type: ApplicationFiled: June 20, 2022Publication date: June 27, 2024Inventors: Steven C. WOO, Dongyun LEE