Abstract: A system is described for prefetching data from a main memory before the data is requested by a processor. The system includes a prefetch buffer having a number of entries to store prefetch reads. Each entry in the prefetch buffer includes a storage area designated for data and address. The system also includes a number of state machines, each state machine to track data phase for each entry in the prefetch buffer. A read request controller is coupled to the prefetch buffer and is configured to receive a read request from the processor or I/O devices and controls dispatching of prefetch requests to a main memory.

Abstract: A method and apparatus for communicating a configuration operation throughout an integrated circuit chip is disclosed. The present invention receives a configuration operation having a configuration word. The configuration word is stored in a defer register until the configuration word can be communicated to one or more target local configuration registers, which are the registers in which the configuration word is to be stored and/or used. During the time period during which the configuration word is stored in the defer register, subsequent operations including operations having configuration data associated with the configuration word are delayed. In one embodiment, operations are caused to retry if a configuration word is stored in the defer register. The configuration data associated with the configuration word is received after the defer register has been cleared. After the configuration data has been received, subsequent operations are blocked for a predetermined period of time.