Abstract: Proximity sensor devices are described that integrate a light emitting diode with a light sensor assembly in a single, compact package. The proximity sensor devices comprise a substrate having a surface. The light emitting diode and light sensor assembly are mounted to the substrate proximate to the surface. The light emitting diode is configured to emit electromagnetic radiation in a limited spectrum of wavelengths, while the light sensor assembly is configured to detect electromagnetic radiation in the limited spectrum of wavelengths emitted by the light emitting diode. An encapsulation layer is formed on the surface over the light emitting diode and light sensor assembly. A trench is formed in the encapsulation layer to receive electromagnetic radiation blocking material configured to block electromagnetic radiation in the limited spectrum of wavelengths to at least partially mitigate crosstalk between the light emitting diode and the light sensor assembly.

Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and a first set of die pads on the device are exposed by forming openings of a first diameter in the photoresist. Pillars of the first diameter are formed by electroplating metal onto the exposed die pads. Then a second photoresist deposited over the first photoresist covers the pillars of the first diameter. Openings of a second diameter are formed in the first and second photoresists to expose a second set of die pads. Pillars of the second diameter are formed by electroplating metal onto the exposed die pads. The photoresists are then removed along with conductive layers on the device used as part of the plating process.

Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and first openings in the photoresist are formed. Metal layers are formed by electroplating metal into the first openings for a first time period. Then the photoresist is patterned to form second openings having a smaller diameter than the first openings. Narrow pillars are formed by electroplating metal into the second openings for a second time period during which the metal is also added to the metal layers in the first openings to form wide pillars having substantially the same height as the narrow pillars. The photoresist is then removed along with conductive layers on the device used as part of the plating process.

Abstract: A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and a first set of die pads on the device are exposed by forming openings of a first diameter in the photoresist. Pillars of the first diameter are formed by electroplating metal onto the exposed die pads. Then a second photoresist deposited over the first photoresist covers the pillars of the first diameter. Openings of a second diameter are formed in the first and second photoresists to expose a second set of die pads. Pillars of the second diameter are formed by electroplating metal onto the exposed die pads. The photoresists are then removed along with conductive layers on the device used as part of the plating process.

Abstract: A bonding pad arrangement and method of bonding a flip-chip semiconductor device to a substrate using copper pillars and solder to join die pads on the flip-chip to substrate pads on the substrate. Each substrate pad has an offset from a respective die pad at specific temperature, the offset for each of the substrate pads is substantially the same, and the offset is determined as a function of the size of the flip-chip device, a difference between a solidification temperature of the solder and the specific temperature, and a difference between a coefficient of thermal expansion of the flip-chip device and a coefficient of thermal expansion of the substrate. Alternatively, the offset for each of the substrate pads is the above-determined offset scaled as a function of a distance the respective die pad is from the centroid of the device.

Abstract: An integrated circuit (IC) package is disclosed comprising a substrate including a plurality of substrate contacts; a semiconductor die including a plurality of die contacts; and a plurality of conductors for providing direct connections between substrate contacts and die contacts, respectively. By having the conductors directly route the connections between the die contacts and substrate contacts, many improvements may be realized including, but not limited to, improved package routing capabilities, reduced die and/or package size, improved package reliability, improved current handling capacity, improved speed, improved thermal performance, and lower costs.

Abstract: Proximity sensor devices are described that integrate a light emitting diode with a light sensor assembly in a single, compact package. The proximity sensor devices comprise a substrate having a surface. The light emitting diode and light sensor assembly are mounted to the substrate proximate to the surface. The light emitting diode is configured to emit electromagnetic radiation in a limited spectrum of wavelengths, while the light sensor assembly is configured to detect electromagnetic radiation in the limited spectrum of wavelengths emitted by the light emitting diode. An encapsulation layer is formed on the surface over the light emitting diode and light sensor assembly. A trench is formed in the encapsulation layer to receive electromagnetic radiation blocking material configured to block electromagnetic radiation in the limited spectrum of wavelengths to at least partially mitigate crosstalk between the light emitting diode and the light sensor assembly.

Abstract: Disclosed are systems and methods for improving the thermal performance of integrated circuit packages. Aspects of the present invention include improved thermal package structures and methods for producing the same through the application of one or more thermal spreaders in the package. In embodiments, a thermal spreader is incorporated in a semiconductor chip package between a semiconductor die and its die pad. By including a thermal spreader in an IC package, the package can handle higher levels of power while maintaining approximately the same temperature of the package or can reduce the temperature of the package when operating at the same power level, as compared to a package without a thermal spreader.

Abstract: An IC package including one or more z-axis interconnects for performing at least in part the fan-in/fan out interconnection for electrically coupling contacts of semiconductor die to external contacts of the package. The z-axis interconnect comprises a matrix of electrically conducting elements extending from the top to the bottom surface of the interconnect. Each conductive element is internally insulated from other conductive elements of the matrix. The semiconductor contacts may be electrically coupled to separate portions of the matrix by way of electrical connections to the top of the z-axis interconnect. Similarly, the external contacts of the package may be electrically coupled to the same separate portions of the matrix by way electrical connections to the bottom of the interconnect. The z-axis interconnect improves the miniaturization, integration, thermal and electrical performance of IC packages.

Abstract: Disclosed are systems and methods for improving the thermal performance of integrated circuit packages. Aspects of the present invention include improved thermal package structures and methods for producing the same through the application of one or more thermal spreaders in the package. In embodiments, a thermal spreader is incorporated in a semiconductor chip package between a semiconductor die and its die pad. By including a thermal spreader in an IC package, the package can handle higher levels of power while maintaining approximately the same temperature of the package or can reduce the temperature of the package when operating at the same power level, as compared to a package without a thermal spreader.

Abstract: Disclosed are systems and methods for improving the thermal performance of integrated circuit packages. Aspects of the present invention include improved thermal package structures and methods for producing the same through the application of one or more thermal spreaders in the package. In embodiments, a thermal spreader is incorporated in a semiconductor chip package between a semiconductor die and its die pad. By including a thermal spreader in an IC package, the package can handle higher levels of power while maintaining approximately the same temperature of the package or can reduce the temperature of the package when operating at the same power level, as compared to a package without a thermal spreader.

Abstract: An integrated circuit (IC) package is disclosed comprising a substrate including a plurality of substrate contacts; a semiconductor die including a plurality of die contacts; and a plurality of conductors for providing direct connections between substrate contacts and die contacts, respectively. By having the conductors directly route the connections between the die contacts and substrate contacts, many improvements may be realized including, but not limited to, improved package routing capabilities, reduced die and/or package size, improved package reliability, improved current handling capacity, improved speed, improved thermal performance, and lower costs.

Abstract: IC package structures for high power dissipation and low RDSon. The package can be considered an inverted QFN package typically manufactured from a double etched lead frame that is then formed (stamped) to receive the electronic devices for connection and wire bonding to the lead frame leads, followed by potting and dicing. Using a split paddle allows the packaging of multiple, electrically isolated power devices. The package is particularly advantageous for packaging vertical power MOSFET devices. Various embodiments are disclosed.

Abstract: Disclosed are systems and methods for improving the thermal performance of integrated circuit packages. Aspects of the present invention include improved thermal package structures and methods for producing the same through the application of one or more thermal spreaders in the package. In embodiments, a thermal spreader is incorporated in a semiconductor chip package between a semiconductor die and its die pad. By including a thermal spreader in an IC package, the package can handle higher levels of power while maintaining approximately the same temperature of the package or can reduce the temperature of the package when operating at the same power level, as compared to a package without a thermal spreader.