Abstract: A self-timing, passive, chemical dosimeter. The dosimeter includes a sampling media and electronics supported by a cassette. The sampling media is configured to absorb volatile organic compounds, semivolatile organic compounds, or both, while the electronics are configured to record a time of exposure. The dosimeter further includes an actuator having a closed position and an open position. In the closed position, the actuator resists exposure of the sampling media to volatile organic compounds, semivolatile organic compounds, or both, and in the open position, the actuator permits exposure of the sampling media to volatile organic compounds, semivolatile organic compounds, or both. The actuator is configured to operate the electronics for recording time of exposure.

Abstract: A self-timing, passive, chemical dosimeter. The dosimeter includes a sampling media and electronics supported by a cassette. The sampling media is configured to absorb volatile organic compounds, semivolatile organic compounds, or both, while the electronics are configured to record a time of exposure. The dosimeter further includes an actuator having a closed position and an open position. In the closed position, the actuator resists exposure of the sampling media to volatile organic compounds, semivolatile organic compounds, or both, and in the open position, the actuator permits exposure of the sampling media to volatile organic compounds, semivolatile organic compounds, or both. The actuator is configured to operate the electronics for recording time of exposure.

Abstract: A memory system for a computer detects data errors, address errors and operation errors to increase the reliability of data stored in the memory system. Address errors are detected by encoding address parity information into the data check field of each memory location. A signal is generated in each memory module indicating the status of operations of that memory module and is transmitted to the processor subsystem of the computer for comparison with a signal indicating the status of operations of the processor subsystem to insure that all memory modules and the memory control in the processor are receiving the same commands.

Abstract: A plurality of multiprocessor systems is arranged in a high speed network to allow any processor in one system to communicate with any processor in another system. The network is configured as a multi-node dual bidirectional ring having a multiprocessor system at each node. Packets of information may be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor in a selected direction between each successive transfer between neighboring nodes. The buffer locations are managed so that they can request an adjacent node to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.

Abstract: A plurality of multiprocessor systems is arranged in a high speed network to allow any processor in one system to communicate with any processor in another system. The network may be configured as a multi-node dual bidirectional ring having a multiprocessor system at each node. Packets of information may be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor in a selected direction between each successive transfer between neighboring nodes. The buffer locations are managed so that a node can request an adjacent node to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.