Abstract: A low distortion differential amplifier circuit includes a primary differential circuit stage and a secondary differential circuit stage. The primary differential circuit stage includes first and second transistors each having a first current source coupled to the emitters of the first and second transistors. A first load device is coupled to the collector of the second transistor. The secondary differential circuit stage includes third and fourth transistors. A second current source is coupled to the emitters of the third and fourth transistors. The bases of the third and fourth transistors are coupled to the collectors of the first and second transistors, respectively. A second load device is coupled to the collector of the fourth transistor. A fifth transistor has its emitter and collector coupled to a supply voltage conductor and the base of the third transistor, respectively.

Abstract: A push-pull amplifier circuit includes an NPN pullup transistor and an pulldown transistor, an emitter of the pullup transistor being coupled to a collector of the pulldown transistor. A first resistor is coupled between an output conductor and the emitter of the pullup transistor, and a second resistor is coupled between an emitter of the pulldown transistor and a supply voltage. A bias circuit includes a phase splitting transistor having an emitter coupled to a constant bias current source and a base of the pullup transistor, a collector coupled to a base of the pulldown transistor, and a control electrode coupled to an input signal. The phase splitting transistor steers a portion of the bias current into a first conductor connected to the base of the pullup transistor and a portion of the bias current into a second conductor connected to the base of the pulldown transistor in response to an input signal applied to the control electrode of the phase splitting transistor.

Abstract: A differential common base amplifier circuit includes first and second source follower field effect transistors that apply a differential input signal between the emitters of first and second bipolar transistors having a common base connection. An output circuit connected to the collector of the first bipolar transistor includes a bipolar emitter follower transistor having its emitter connected to a first field effect transistor which is connected to the emitter of the emitter follower transistor. The gate of the first field effect transistor is connected to the gate of one of the source follower field effect transistors. Process-caused variations in the gate to source voltage characteristic of the second source follower field effect transistor and the first field effect transistor are applied equally to the emitter and collector of the second bipolar transistor. This avoids input offset errors due to base width variations in the second bipolar transistor.

Abstract: In a circuit in which a common-source junction field effect transistor (JFET) is cascoded with a JFET element, current diversion or division circuits are used to divert a majority of the current passing through the input amplifier stage so that it bypasses the cascode FET without compromising the primary circuit function. The bypassing function is achieved by a current mirror, a current mirror-like circuit, or similar devices such as current sources, current splitters and the like and the circuits may be ratioed to more precisely control the bypass current by the use of emitter area scaling, ratioed emitter degeneration resistors, or both. The resultant cascode circuit is relatively noise-free and can easily be implemented into a monolithic integrated circuit without using excess or unrealistic die areas.