Abstract: An electronic assembly perform data storage operations on behalf of a set of storage processors (SPs). The electronic assembly includes an enclosure, and a set of peripheral component interconnect express (PCIe) switches which installs within the enclosure. The set of PCIe switches is constructed and arranged to connect to the set of SPs while the set of SPs is external to the enclosure. The electronic assembly further includes a set of data storage devices which installs within the enclosure. The set of data storage devices is constructed and arranged to persistently store data on behalf of the set of SPs via PCIe-based communications through the set of PCIe switches.

Abstract: A method performed by a storage system includes a first storage processor performing input/output (IO) requests on a first one or more logical units, and a second storage processor performing IO requests on a second one or more logical units. If the first storage processor fails, the third storage processor performs the IO requests on the first one or more logical units. If the second storage processor fails, the fourth storage processor performing the IO requests on the second one or more logical units.

Abstract: A storage network includes at least one storage processor. At least one switch is coupled to the at least one storage processor. At least one nontransparent bridge is coupled to the at least one switch. The at least one nontransparent bridge includes at least one addressable endpoint. At least one storage device is coupled to the nontransparent bridge. At least one baseboard management controller is coupled to the at least one addressable endpoint.

Abstract: A method, computer program product, and computing system for receiving, on a baseboard management controller coupled to an addressable endpoint of a non-transparent bridge included within a storage network, a plurality of condition messages concerning one or more components of the storage network. The plurality of condition messages are filtered into critical condition messages and noncritical condition messages.

Abstract: A method of caching data includes: A. mirroring data processed by a first storage processor and a second storage processor between a first memory device of the first storage processor and a second memory device of the second storage processor; B. each of the first storage processor and the second storage processor monitoring an availability of the other of the first storage processor and the second storage processor; C. copying data stored in the first memory device to a third memory device and mirroring data processed by the first storage processor between the first memory device and the third memory device when the second storage processor becomes unavailable to the first storage processor; and D. copying data from the first memory device to the second memory device and mirroring data processed by the first storage processor and the second storage processor between the first memory device and the second memory device when the second storage processor becomes available to the first storage processor.

Abstract: A data storage system includes a first storage processor including a first memory device; a second storage processor including a second memory device; and a third memory device coupled to the first storage processor and the second storage processor. The first and second storage processors are interconnected to enable mirroring of data between the first memory device and the second memory device. During a first mode of operation, data processed by the first storage processor and the second storage processor is mirrored between the first memory device and the second memory device and, during a second mode of operation, data processed by the first storage processor is mirrored from the first memory device to the third memory device.

Abstract: A data storage system having a pair of CPU modules each one of having a port coupled to a host computer/server and a storage medium for transferring data during an IO transfer. Each one of the modules produces different types of reset signals, one of such types being a software reset signal produced during a software upgrade of the module and other types being produced for events other than during a software upgrade, The other types produced by a first one of the modules disables the port of the first one of the modules; whereas, in response the software reset signal produced by the first one of the modules during an IO transfer, a second one of the modules couples the port of the first one of the modules to the second one of the modules to enable the IO transfer to be processed by the second one of the modules.

Abstract: Flow control settings are configured. Credit settings for credit types of input/output interconnect ports are programmed at a low value. The system type of a system containing the input/output interconnect ports is detected. The credit settings are reprogrammed in accordance with the system type.

Abstract: Described is an electronics system and method for marking and faulting I/O ports of an I/O module in the electronics system. Each I/O port has an associated light-emitting system that is capable of emitting a plurality of different colors. At least one color is blinked at a first rate to produce a first status indicator for the I/O port. Each color of the different colors is alternately blinked at a second rate to produce a second status indicator for the I/O port. One of the status indicators is for marking the I/O port and the other status indicator is for faulting the I/O port. In one embodiment, the light-emitting system includes a plurality of differently colored LEDs. In another embodiment, the light-emitting system includes only one multicolor LED. Various I/O technologies including Fiber Channel, Fiber Connectivity, Ethernet, serial attached SCSI, IPsec, Infiniband, and iSCSI, can implement marking and faulting.

Abstract: Disclosed are ways of providing a highly flexible high availability storage system. Disk drive carriers for insertion into enclosures in a storage system include several disk drives. The enclosures accept carriers that include drives of different sizes, and drives compatible with different storage technologies, for instance Fibre Channel, SATA, or SAS. Drives oriented in their carriers in a manner that allows them to be connected to a common medium via identical flex circuits that are configured based on the orientation of the drives. Redundant controllers include redundant serial buses for transferring management information to the carriers. The carriers include a controller for monitoring the multiple serial buses and producing storage technology specific management commands for the disk drives.

Abstract: Described are electronics systems and methods for distributing a limited number of lanes of a PCI Express-based processor (CPU) module among a plurality of PCI Express-based I/O modules with which the CPU module is in communication. The CPU module receives a code from each I/O module over a sideband interface between that I/O module and the CPU module. The coded signal represents a link-width capability of the I/O module. The CPU module is configured to allocate a link width to each I/O module based on the fixed number of lanes and the link-width capability as represented by the coded signal received from that I/O module. The link between CPU module and each I/O module is trained in accordance with the link width allocated to that I/O module.

Abstract: Communications settings are managed. System characteristics are determined that affect communications on a high speed transmission link between nodes. The system characteristics includes system hardware information and physical characteristics of a cable. Tuning information is derived from the system characteristics. At least some of the tuning information is communicated between the nodes.

Abstract: Described is an electronics enclosure having a midplane, a first field-replaceable CPU (central processing unit) module, and a second field-replaceable CPU module. Each CPU module is independently pluggable into and removable from the midplane. Each CPU module is configurable into either one of a first configuration and a second configuration, wherein the CPU modules operate independently as separate CPU modules when configured according to the first configuration and cooperate as a unitary CPU module when configured according to the second configuration.

Abstract: Described are electronics enclosures having an I/O (input/output) module, a CPU (central processing unit) module having a root complex, and a pluggable, field-replaceable interconnect module electrically connected to the root complex of the CPU module by a first set of differential signal pairs and to the I/O module by a second set of differential signal pairs. The field-replaceable interconnect module provides a serialized communication path between the first and second sets of differential signal pairs for carrying serialized differential signaling corresponding to communications exchanged between the root complex of the CPU module and the I/O module.

Abstract: Described is an enclosure that is configurable to perform either in-band or out-of-band enclosure management. The enclosure includes a midplane, a processor blade, and a management module. The processor blade has program code for collecting management information from other components in the enclosure. If the enclosure is configured for in-band enclosure management, the processor blade executes the program code to collect the management information. If the enclosure is configured for out-of-band enclosure management, the management module is configured to execute program code for collecting the management information instead of the processor blade.

Abstract: System components are managed. Based on a first communication path to a component, first identification information for the component is determined. Based on a second communication path to the component, second identification information for the component is determined. Based on the first identification information and the second identification information, an identity for the component is determined. Based on the identity, a set of tests is performed on the component. Based on the failure rate of the set of tests, it is concluded that another component on the first communication path is faulty.

Abstract: A data storage system includes a first storage processor for storing and retrieving data from a data storage array for at least one host computer; a second storage processor, coupled to the first storage processor by a communication link, for storing and retrieving data from the data storage array for the at least one host computer; a number M of multiplexers, M being greater than one, each of the multiplexers being coupled to the first storage processor and the second storage processor for receiving data signals from the first storage processor and the second storage processor and transmitting the data signals to a disk drive device; a number A of arbiters, each being coupled to the first storage processor, the second storage processor and a number N of the plurality of multiplexers, for receiving arbiter control signals from the first storage processor and the second storage processor and transmitting multiplexer control signals to each of the number N of the plurality of multiplexers; and a midplane device

Abstract: A data storage system includes a disk drive array including a plurality of disk drives; a first storage processor for controlling the operation of the data storage system; a second storage processor for controlling the operation of the data storage system; a first arbiter for controlling communication of data from the first storage processor and the second storage processor to a first group of disk drives of the disk drive array; and a second arbiter for controlling communication of data from the first storage processor and the second storage processor to a second group of disk drives of the disk drive array. Selected data is redundantly stored on disk drives in the first group of disk drives and the second group of disk drives, such that, upon failure of the first arbiter, the selected data is available to the first storage processor and the second storage processor through the second arbiter.

Abstract: Disk drive status is managed. A detection is made that a disk drive has asserted its Enable Bypass signal. It is determined whether the drive has asserted and de-asserted its Fault LED signal in a pattern of transitions signifying that the drive cannot operate at a specified data rate.

Abstract: Apparatus for use in managing disk drive spinup includes a plurality of disk drives newly inserted into a data storage system enclosure that is in an already powered up steady state. The apparatus also includes first and second control cards in the enclosure, and first control logic operable to cause the first and second control cards to coordinate to cause the disk drives to spin up in stages.