Patents by Inventor Steven D. Theiss

Steven D. Theiss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080121877
    Abstract: Electronic devices such as transistors are disclosed. The electronic device includes an electrically conductive gate electrode, an anodized layer disposed on the gate electrode, a dielectric layer disposed on the anodized layer, and a semiconductor oxide layer that has a channel region. The channel region is disposed on the dielectric layer and has an internal resistance. The internal resistance of the channel can change when an electrical signal is applied to the gate electrode.
    Type: Application
    Filed: November 27, 2006
    Publication date: May 29, 2008
    Inventors: David A. Ender, Michael W. Bench, Steven D. Theiss, Jonathan A. Nichols
  • Publication number: 20080121528
    Abstract: Method of fabricating electronic devices is disclosed. The method includes the steps of forming an anodized layer that has a thickness greater than a desired thickness, and forming an electrically conductive layer on the anodized layer. The method further includes the steps of removing the conductive layer in a selected area to expose the anodized layer, and removing the exposed anodized layer until the anodized layer in the exposed area has the desired thickness.
    Type: Application
    Filed: November 27, 2006
    Publication date: May 29, 2008
    Inventors: Michael W. Bench, Steven D. Theiss, Grace L. Ho
  • Patent number: 7298084
    Abstract: Methods and displays utilize row and column drivers with ZnO channels that control pixel transistors with ZnO channels, which in turn address OLEDs of an array to produce images of a display screen. A display backplane including the ZnO row and column drivers and the OLEDs may be constructed by utilizing aperture masking or a combination of photolithography and aperture masking. Monolithic integration of the ZnO row and column drivers together with the ZnO pixel transistors is thereby achieved.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: November 20, 2007
    Assignee: 3M Innovative Properties Company
    Inventors: Paul F. Baude, Steven D. Theiss, Michael A. Haase, Eric W. Hemmesch
  • Patent number: 7245151
    Abstract: Logic circuitry is powered by a partially rectified alternating current (ac) waveform. The waveform is partially rectified in the sense that it does not provide a clean, primarily dc power signal. Instead, it is possible to power logic circuitry with a waveform that includes a substantial ac component. The partially rectified ac waveform may be applied to logic circuitry incorporating thin film transistors based on amorphous or polycrystalline organic semiconductors, inorganic semiconductors or combinations of both.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: July 17, 2007
    Assignee: 3M Innovative Properties Company
    Inventors: Paul F. Baude, Michael A. Haase, Steven D. Theiss
  • Patent number: 7112846
    Abstract: Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: September 26, 2006
    Assignee: The Regents of the University of California
    Inventors: Jesse D. Wolfe, Steven D. Theiss, Paul G. Carey, Patrick M. Smith, Paul Wickboldt
  • Patent number: 7078937
    Abstract: Logic circuitry is powered by a partially rectified alternating current (ac) waveform. The waveform is partially rectified in the sense that it does not provide a clean, primarily dc power signal. Instead, it is possible to power logic circuitry with a waveform that includes a substantial ac component. The partially rectified ac waveform may be applied to logic circuitry incorporating thin film transistors based on amorphous or polycrystalline organic semiconductors, inorganic semiconductors or combinations of both.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: July 18, 2006
    Assignee: 3M Innovative Properties Company
    Inventors: Paul F. Baude, Michael A. Haase, Steven D. Theiss
  • Patent number: 6855636
    Abstract: The present invention provides a process for selectively thermally transferring insulators onto organic electroluminescent stacks or layers to electronically isolate adjacent devices upon deposition of electrode material. This can allow the formation of top electrodes for a plurality of organic electroluminescent devices on a substrate via one deposition step to form a single common top electrode or a plurality of electrodes patterned by shadowing due to the presence of the insulators.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: February 15, 2005
    Assignee: 3M Innovative Properties Company
    Inventors: Steven D. Theiss, Ha T. Le, William A. Tolbert, Martin B. Wolk, Paul F. Baude
  • Patent number: 6806520
    Abstract: A method for making transistors comprises depositing source electrode and drain electrode features onto a substrate through a single aperture in a stationary shadow mask, said aperture having at least two opposing edges; wherein the shapes of the features are defined by the aperture and location of source materials in relation to the substrate.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: October 19, 2004
    Assignee: 3M Innovative Properties Company
    Inventors: Steven D. Theiss, Michael A. Haase, Silva K. Theiss
  • Publication number: 20040106262
    Abstract: A method for making transistors comprises depositing source electrode and drain electrode features onto a substrate through a single aperture in a stationary shadow mask, said aperture having at least two opposing edges; wherein the shapes of the features are defined by the aperture and location of source materials in relation to the substrate.
    Type: Application
    Filed: November 21, 2003
    Publication date: June 3, 2004
    Applicant: 3M Innovative Properties Company
    Inventors: Steven D. Theiss, Michael A. Haase, Silva K. Theiss
  • Publication number: 20040087165
    Abstract: The present invention provides a process for selectively thermally transferring insulators onto organic electroluminescent stacks or layers to electronically isolate adjacent devices upon deposition of electrode material. This can allow the formation of top electrodes for a plurality of organic electroluminescent devices on a substrate via one deposition step to form a single common top electrode or a plurality of electrodes patterned by shadowing due to the presence of the insulators.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Applicant: 3M Innovative Properties Company
    Inventors: Steven D. Theiss, Ha T. Le, William A. Tolbert, Martin B. Wolk, Paul F. Baude
  • Publication number: 20040016926
    Abstract: Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.
    Type: Application
    Filed: July 16, 2003
    Publication date: January 29, 2004
    Applicant: The Regents of the University of California
    Inventors: Jesse D. Wolfe, Steven D. Theiss, Paul G. Carey, Patrick M. Smith, Paul Wickboldt
  • Patent number: 6667215
    Abstract: A method for making transistors comprises depositing source electrode and drain electrode features onto a substrate through a single aperture in a stationary shadow mask, said aperture having at least two opposing edges; wherein the shapes of the features are defined by the aperture and location of source materials in relation to the substrate.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: December 23, 2003
    Assignee: 3M Innovative Properties
    Inventors: Steven D. Theiss, Paul F. Baude, Michael A. Haase, Silva K. Theiss
  • Publication number: 20030207505
    Abstract: A method for making transistors comprises depositing source electrode and drain electrode features onto a substrate through a single aperture in a stationary shadow mask, said aperture having at least two opposing edges; wherein the shapes of the features are defined by the aperture and location of source materials in relation to the substrate.
    Type: Application
    Filed: May 2, 2002
    Publication date: November 6, 2003
    Applicant: 3M Innovative Properties Company
    Inventors: Steven D. Theiss, Paul F. Baude, Michael A. Haase, Silva K. Theiss
  • Patent number: 6642085
    Abstract: Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: November 4, 2003
    Assignee: The Regents of the University of California
    Inventors: Jesse D. Wolfe, Steven D. Theiss, Paul G. Carey, Patrick M. Smith, Paul Wickboldt
  • Patent number: 6436739
    Abstract: Thick adherent dielectric films deposited on plastic substrates for use as a thermal barrier layer to protect the plastic substrates from high temperatures which, for example, occur during laser annealing of layers subsequently deposited on the dielectric films. It is desirable that the barrier layer has properties including: a thickness of 1 &mgr;m or greater, adheres to a plastic substrate, does not lift-off when cycled in temperature, has few or no cracks and does not crack when subjected to bending, resistant to lift-off when submersed in fluids, electrically insulating and preferably transparent. The thick barrier layer may be composed, for example, of a variety of dielectrics and certain metal oxides, and may be deposited on a variety of plastic substrates by various known deposition techniques. The key to the method of forming the thick barrier layer on the plastic substrate is maintaining the substrate cool during deposition of the barrier layer.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: August 20, 2002
    Assignee: The Regents of the University of California
    Inventors: Paul Wickboldt, Albert R. Ellingboe, Steven D. Theiss, Patrick M. Smith