Abstract: A differential two-stage Miller compensated amplifier system with capacitive level shifting includes a first stage differential transconductance amplifier including first and second output nodes and an output common mode voltage, a second stage differential transconductance amplifier including non-inverting and inverting inputs and outputs and an input common mode voltage, and a level shifting capacitor circuit coupled between the first and second output nodes and the non-inverting and inverting inputs for level shifting between the output common mode voltage of the first stage and the input common mode voltage of the second stage.

Abstract: A suturing device allows a physician to remotely seal an incision in a blood vessel or other biological tissue. The device comprises an elongated tubular body having a distal portion which is adapted to be inserted percutaneously through the incision and into the blood vessel. The distal portion has first and second retractable arms which extend from the distal portion of the body and releasably hold a suture within the blood vessel. First and second retractable needles, each of which is configured to catch the suture from a respective arm, are provided along the body proximal to the retractable arms. The arms and the needles are remotely movable by the physician using a handle or other control mechanism provided at a distal portion of the device. In operation, the arms are initially deployed within the blood vessel to hold the ends of the suture beyond the circumference of the tubular body.

Abstract: Methods and apparatus are provided for closing incisions within biological tissue. In one embodiment, a device and method are provided for suturing biological tissue, such as, for example, an organ or blood vessel. The suturing apparatus is particularly well suited for suturing an incision made in an artery, such as the femoral artery, following a catheterization procedure. The device eliminates the need to apply pressure to a patient's thigh for an extended period of time, and eliminates many of the complications and costs associated with the creation of a thrombus patch. In addition, the device comprises an improved handle portion which enables the physician to quickly and easily apply suture. The handle portion is very reliable and easy to manipulate. The suturing may be used in combination with existing catheter sheath introducers.

Abstract: One embodiment of the invention is directed to a method comprising an act of performing digital correction of an offset in a system comprising an analog-to-digital converter (ADC) having a usable input range that is greater than a nominal input range, wherein the offset exists at an input of the ADC. Another embodiment of the invention is directed to a system comprising an ADC having a usable input range that is greater than a nominal input range, wherein an offset exists at an input of the ADC and the offset is corrected using digital correction.

Abstract: A suturing apparatus comprises an elongated body, at least one arms movable relative to the elongated body and at least one needle movable relative to the elongated body. The arm releasably holds an end portion of a length of suture. The arm has a sharp end portion adapted to pierce an inner surface of a wall of a biological structure and pass an end portion of the suture through the inner surface. The needle is adapted to pierce the inner surface of such biological structure at a location proximal to the location where the end portion of the suture was inserted. The needle captures an end portion of the suture from the arm and draws the end portion of the suture back through the inner surface. The end of the suture is then drawn out of the biological structure by removing the elongated body.

Abstract: One embodiment of the invention is directed to a method of extending the input range of an analog-to-digital converter (ADC) having a nominal input voltage range. The method comprises an act of mapping an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code. Another embodiment of the invention is directed to an apparatus comprising an ADC having a nominal input voltage range, wherein the ADC is adapted to map an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code.

Abstract: One embodiment of the invention is directed to a method of extending the input range of an analog-to-digital converter (ADC) having a nominal input voltage range. The method comprises an act of mapping an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code. Another embodiment of the invention is directed to an apparatus comprising an ADC having a nominal input voltage range, wherein the ADC is adapted to map an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code.

Abstract: One embodiment of the invention is directed to a method comprising an act of performing digital correction of an offset in a system comprising an analog-to-digital converter (ADC) having a usable input range that is greater than a nominal input range, wherein the offset exists at an input of the ADC. Another embodiment of the invention is directed to a system comprising an ADC having a usable input range that is greater than a nominal input range, wherein an offset exists at an input of the ADC and the offset is corrected using digital correction.

Abstract: An offset correction circuit loop with summing nodes, a variable gain transconductance amplifier and capacitor. The input to the loop is sent to a first summing node and then to a separate circuit. The output of the separate circuit is sent to the output of the loop and to the input of a second summing node. The second summing node subtracts the circuit output from a reference voltage and sends the result to the transconductance amplifier which outputs a corrective current which is then integrated onto the capacitor to produce a corrective input offset voltage estimate.

Abstract: In one embodiment, an image sensor includes a linear pixel array and array readout lines, wherein the linear pixel array includes a group of pixels arranged in a row, and each array readout line is selectively coupled to an output of at least one pixel included in the group of pixels. In another embodiment, an image sensor includes a linear pixel array and an array readout line, wherein the linear pixel array includes a first group of pixels, sensitive to a first color of light, arranged in a first row, and a second group of pixels, sensitive to a second color of light, arranged in a second row, and the array readout line is selectively coupled to outputs of pixels included in the first group of pixels and outputs of pixels included in the second group of pixels.

Abstract: In one embodiment, an image sensor includes an area pixel array, column readout lines, and array readout lines, wherein the area pixel array includes columns of pixels, each including pixels of a first type, each column readout line is selectively coupled to outputs of the pixels of the first type that are included in a respective column of pixels, and each array readout line is selectively coupled to at least one of the first column readout lines. In another embodiment, an image sensor includes a pixel array, column readout lines, and array readout lines, wherein the pixel array includes a row of pixels which includes pixels of a first type, each column readout line is selectively coupled to an output of a respective pixel of the first type that is included in the row of pixels, and each array readout line is selectively coupled to at least one of the column readout lines.

Abstract: In one embodiment, an image sensor includes an area pixel array, column readout lines, and array readout lines, wherein the area pixel array includes columns of pixels, each including pixels of a first type, each column readout line is selectively coupled to outputs of the pixels of the first type that are included in a respective column of pixels, and each array readout line is selectively coupled to at least one of the first column readout lines. In another embodiment, an image sensor includes a pixel array, column readout lines, and array readout lines, wherein the pixel array includes a row of pixels which includes pixels of a first type, each column readout line is selectively coupled to an output of a respective pixel of the first type that is included in the row of pixels, and each array readout line is selectively coupled to at least one of the column readout lines.

Abstract: A switched capacitor correlated double sampling circuit includes an op amp, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase and the feedback capacitor receives the signal charge from the input capacitor. No sampling switch is located between the input capacitor and the input terminal.