Abstract: This invention is a signal input/output design tool for integrated circuit input/output design. The connectivity capacity of at least multiplexer connecting internal signals and external lines is expressed as a first set of Boolean expressions. The desired connectivity between internal signals and external lines is expressed is provided by a designer. A programmed general purpose computer expresses the desired connectivity as a second set of Boolean expressions and determines whether said first set of Boolean expressions and said second set of Boolean expressions are Boolean satisfiable. If satisfiable, the design tool generates control signals to configure the at least one multiplexer to achieve the desired connectivity. If not satisfiable, the design tool generates a report indicating which portions of the desired connectivity are achievable and which are not.

Abstract: This invention is a signal input/output design tool for integrated circuit input/output design. The connectivity capacity of at least multiplexer connecting internal signals and external lines is expressed as a first set of Boolean expressions. The desired connectivity between internal signals and external lines is expressed is provided by a designer. A programmed general purpose computer expresses the desired connectivity as a second set of Boolean expressions and determines whether said first set of Boolean expressions and said second set of Boolean expressions are Boolean satisfiable. If satisfiable, the design tool generates control signals to configure the at least one multiplexer to achieve the desired connectivity. If not satisfiable, the design tool generates a report indicating which portions of the desired connectivity are achievable and which are not.

Abstract: A video display system, such as useful in video surveillance applications, is disclosed. The system includes a video decoder (20) having a common output data port (27) at which it presents interleaved data streams (DSA, DSB). The interleaved data streams (DSA, DSB) may correspond to multiple scalings of a processed video input signal, for example as received from a surveillance camera (C1, C2, C3, C4). The video decoder (20) also outputs multiple clock signals (CLKA, CLKB), each of which are synchronous with a corresponding one of the interleaved data streams (DSA, DSB). This enables a common data port (27) to output multiple data streams (DSA, DSB), while individual destinations (30A, 30B) of the data streams (DSA, DSB) can continue to operate at legacy clock rates.

Abstract: The pixels of an image sensor array can be readout (84, 85) in m×n blocks (m, n) that are compatible with the operation of a desired image compression algorithm (14), thereby reducing the amount of memory required by the image compression algorithm.

Abstract: The invention provides for the filtering of pixel defects from CMOS imagers. The invention comprises scanning each of a plurality of pixels within a block (420), and designating a pixel as a process pixel (430). The process pixel is then compared to adjacent pixels to see if the process pixel value deviates significantly from an adjacent pixel value (450), to determine if error correction is needed.

Abstract: The pixels of an image sensor array can be readout (84, 85) in m×n blocks (m, n) that are compatible with the operation of a desired image compression algorithm (14), thereby reducing the amount of memory required by the image compression algorithm.