Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Abstract: In one example, a method comprises erasing at the same time a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal, by turning on an erase gate enable transistor coupled to erase gate terminals of the word of non-volatile memory cells.

Abstract: This invention pertains to fused ring compounds of Formula (I), as further detailed herein, which are used for the inhibition of Ras proteins, as well as compositions comprising these compounds and methods of treatment by their administration.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell columns, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

Abstract: In one example, a system comprises a neural network array of non-volatile memory cells arranged in rows and columns; and a logical cell comprising a first plurality of non-volatile memory cells in a first row of the array and a second plurality of non-volatile memory cells in a second row adjacent to the first row; wherein the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells are configured as one or more coarse cells and one or more fine cells.

Abstract: Numerous embodiments are provided for compensating for drift error in non-volatile memory cells within a VMM array in an analog neuromorphic memory system. For example, in one embodiment, a circuit is provided for compensating for drift error during a read operation, the circuit comprising a data drift monitoring circuit coupled to the array for generating an output indicative of data drift; and a bitline compensation circuit for generating a compensation current in response to the output from the data drift monitoring circuit and injecting the compensation current into one or more bitlines of the array.

Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

Abstract: Provided herein are aza-tetracyclic oxazepinyl compounds useful in the treatment of cancers.

Abstract: Provided are fused ring compounds of Formula (I), Formula (II), or Formula (III), as further detailed herein, which are used for the inhibition of Ras proteins, as well as compositions comprising these compounds and methods treatment by their administration.

Abstract: This invention pertains to fused ring compounds of Formula (I), as further detailed herein, which are used for the inhibition of Ras proteins, as well as compositions comprising these compounds and methods of treatment by their administration.

Abstract: Provided are fused ring compounds of Formula (I), Formula (II), or Formula (III), as further detailed herein, which are used for the inhibition of Ras proteins, as well as compositions comprising these compounds and methods treatment by their administration.

Abstract: Provided herein are tetracyclic oxazepinyl compounds useful in the treatment on cancers.

Abstract: The present invention provides compounds, including resolved enantiomers, resolved diastereomers, solvates and pharmaceutically acceptable salts thereof, comprising the Formula I: Also provided are methods of using the compounds of this invention as AKT protein kinase inhibitors and for the treatment of hyperproliferative diseases such as cancer.

Abstract: Compounds having the formula I wherein R1, X1, X2, X3 and X4 as defined herein are inhibitors of ERK kinase. Also disclosed are compositions and methods for treating hyperproliferative disorders.

Abstract: This invention pertains to fused ring compounds of Formula (I), as further detailed herein, which are used for the inhibition of Ras proteins, as well as compositions comprising these compounds and methods of treatment by their administration.

Abstract: The invention is concerned with the compounds of formula I or II: and salts thereof. In addition, the present invention relates to methods of manufacturing and methods of using the compounds of formula I or II as well as pharmaceutical compositions containing such compounds. The compounds may be useful in treating diseases and conditions mediated by TRPA1, such as pain.

Abstract: This invention pertains to fused ring compounds of Formula (I), as further detailed herein, which are used for the inhibition of Ras proteins, as well as compositions comprising these compounds and methods of treatment by their administration.