Patents by Inventor Steven Do

Steven Do has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240383915
    Abstract: Provided herein are acyclic oxazepinyl compounds useful in the treatment on cancers.
    Type: Application
    Filed: April 6, 2022
    Publication date: November 21, 2024
    Applicant: Genentech, Inc.
    Inventors: Lewis J. GAZZARD, Samantha Alyson GREEN, Elizabeth H. KELLEY, Matthew Leo LANDRY, Sushant MALHOTRA, Benjamin David RAVETZ, Michael SIU, Jack Alexander TERRETT, BinQing WEI, Steven DO, Yun-Xing CHENG, Limin CHENG, Jianfeng XIN, Mingtao HE, Guosheng WU, Yinlei SUN, Cheng SHAO, Aijun LU, Yulai ZHANG
  • Publication number: 20240368186
    Abstract: Provided herein are aza-tetracyclic oxazepinyl compounds useful in the treatment of cancers.
    Type: Application
    Filed: May 28, 2024
    Publication date: November 7, 2024
    Inventors: Matthew Leo Landry, Christian Nilewski, Michael Siu, Elisia Villemure, Yong Wang, BinQing Wei, Melissa Ann Ashley, Steven Do, Lewis John Gazzard, Samantha Alyson Green
  • Patent number: 12131786
    Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: October 29, 2024
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Louisa Schneider, Xian Liu, Steven Lemke, Parviz Ghazavi, Jinho Kim, Henry A. Om'Mani, Hieu Van Tran, Nhan Do
  • Patent number: 12124944
    Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: October 22, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Nhan Do, Mark Reiten
  • Publication number: 20240312517
    Abstract: In one example, a method comprises erasing at the same time a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal, by turning on an erase gate enable transistor coupled to erase gate terminals of the word of non-volatile memory cells.
    Type: Application
    Filed: January 22, 2024
    Publication date: September 19, 2024
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Vipin Tiwari, Nhan Do
  • Patent number: 12084429
    Abstract: This invention pertains to fused ring compounds of Formula (I), as further detailed herein, which are used for the inhibition of Ras proteins, as well as compositions comprising these compounds and methods of treatment by their administration.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: September 10, 2024
    Assignee: Genentech, Inc.
    Inventors: Sushant Malhotra, Jianfeng Xin, Steven Do, Jack Terrett
  • Publication number: 20240282369
    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 22, 2024
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Publication number: 20240274186
    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 15, 2024
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Publication number: 20240274187
    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell columns, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 15, 2024
    Inventors: Hieu Van Tran, STEVEN LEMKE, VIPIN TIWARI, NHAN DO, MARK REITEN
  • Patent number: 12057170
    Abstract: In one example, a system comprises a neural network array of non-volatile memory cells arranged in rows and columns; and a logical cell comprising a first plurality of non-volatile memory cells in a first row of the array and a second plurality of non-volatile memory cells in a second row adjacent to the first row; wherein the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells are configured as one or more coarse cells and one or more fine cells.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: August 6, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Stanley Hong, Stephen Trinh, Thuan Vu, Steven Lemke, Vipin Tiwari, Nhan Do
  • Patent number: 12056601
    Abstract: Numerous embodiments are provided for compensating for drift error in non-volatile memory cells within a VMM array in an analog neuromorphic memory system. For example, in one embodiment, a circuit is provided for compensating for drift error during a read operation, the circuit comprising a data drift monitoring circuit coupled to the array for generating an output indicative of data drift; and a bitline compensation circuit for generating a compensation current in response to the output from the data drift monitoring circuit and injecting the compensation current into one or more bitlines of the array.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: August 6, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Publication number: 20240257880
    Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.
    Type: Application
    Filed: January 31, 2023
    Publication date: August 1, 2024
    Inventors: Louisa Schneider, Xian Liu, Steven Lemke, Parviz Ghazavi, Jinho Kim, Henry A. Om'Mani, Hieu Van Tran, Nhan Do
  • Publication number: 20240025919
    Abstract: Provided herein are aza-tetracyclic oxazepinyl compounds useful in the treatment of cancers.
    Type: Application
    Filed: May 19, 2023
    Publication date: January 25, 2024
    Inventors: Matthew Leo Landry, Christian Nilewski, Michael Siu, Elisia Villemure, Yong Wang, BinQing Wei, Melissa Ann Ashley, Steven Do, Lewis John Gazzard, Samantha Alyson Green
  • Patent number: 11760744
    Abstract: Provided are fused ring compounds of Formula (I), Formula (II), or Formula (III), as further detailed herein, which are used for the inhibition of Ras proteins, as well as compositions comprising these compounds and methods treatment by their administration.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: September 19, 2023
    Assignee: Genentech, Inc.
    Inventors: Aijun Lu, Sushant Malhotra, Alan G. Olivero, Cheng Shao, Yamin Zhang, Steven Do
  • Publication number: 20230089126
    Abstract: This invention pertains to fused ring compounds of Formula (I), as further detailed herein, which are used for the inhibition of Ras proteins, as well as compositions comprising these compounds and methods of treatment by their administration.
    Type: Application
    Filed: December 17, 2021
    Publication date: March 23, 2023
    Inventors: Sushant Malhotra, Jianfeng Xin, Steven Do, Jack Terrett
  • Publication number: 20230002345
    Abstract: Provided are fused ring compounds of Formula (I), Formula (II), or Formula (III), as further detailed herein, which are used for the inhibition of Ras proteins, as well as compositions comprising these compounds and methods treatment by their administration.
    Type: Application
    Filed: August 15, 2019
    Publication date: January 5, 2023
    Inventors: Aijun LU, Sushant Malhotra, Alan G. Olivero, Cheng Shao, Yamin Zhang, Steven Do
  • Publication number: 20220281893
    Abstract: Provided herein are tetracyclic oxazepinyl compounds useful in the treatment on cancers.
    Type: Application
    Filed: February 7, 2022
    Publication date: September 8, 2022
    Applicant: Genentech, Inc.
    Inventors: Lewis J. GAZZARD, Samantha Alyson GREEN, Matthew Leo LANDRY, Sushant MALHOTRA, Michael SIU, Steven DO, Yun-Xing CHENG, Limin CHENG, Jianfeng XIN, Mingtao HE
  • Publication number: 20220226326
    Abstract: The present invention provides compounds, including resolved enantiomers, resolved diastereomers, solvates and pharmaceutically acceptable salts thereof, comprising the Formula I: Also provided are methods of using the compounds of this invention as AKT protein kinase inhibitors and for the treatment of hyperproliferative diseases such as cancer.
    Type: Application
    Filed: August 23, 2021
    Publication date: July 21, 2022
    Applicants: Array BioPharma Inc., Genentech, Inc.
    Inventors: Ian S. Mitchell, James F. Blake, Rui Xu, Nicholas C. Kallan, Dengming Xiao, Keith Lee Spencer, Josef R. Bencsik, Eli M. Wallace, Stephen T. Schlachter, Anna L. Leivers, Jun Liang, Brian Safina, Birong Zhang, Christine Chabot, Steven Do
  • Patent number: 11376260
    Abstract: Compounds having the formula I wherein R1, X1, X2, X3 and X4 as defined herein are inhibitors of ERK kinase. Also disclosed are compositions and methods for treating hyperproliferative disorders.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: July 5, 2022
    Assignee: Genentech, Inc.
    Inventors: Aleksandr Kolesnikov, Steven Do
  • Patent number: 11236068
    Abstract: This invention pertains to fused ring compounds of Formula (I), as further detailed herein, which are used for the inhibition of Ras proteins, as well as compositions comprising these compounds and methods of treatment by their administration.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 1, 2022
    Assignee: Genentech, Inc.
    Inventors: Sushant Malhotra, Jianfeng Xin, Steven Do, Jack Terrett