Patents by Inventor Steven Douglas Posluszny

Steven Douglas Posluszny has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7493357
    Abstract: A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: February 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Harm Peter Hofstee, Kevin Nowka, Steven Douglas Posluszny, Joel Abraham Silberman
  • Patent number: 6941335
    Abstract: A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: September 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Harm Peter Hofstee, Kevin Nowka, Steven Douglas Posluszny, Joel Abraham Silberman
  • Patent number: 6772368
    Abstract: In one embodiment a multiprocessing apparatus includes a first processor and a second processor. Each of the processors have their own data and instruction caches to support independent operation. In a normal mode the processors independently execute separate instruction streams. Each of the processors has a respective signature generator. The system also includes a compare unit coupled to the signature generators. In a high reliability mode, both processors execute the same instruction stream. That is, each processor computes a version of a result for ones of the instructions in the stream. Responsive to the respective versions, the respective signature generators assert signatures to the compare unit, so that a faulting instruction may be detected. In another aspect, each processor has its own respective commit logic.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: August 3, 2004
    Assignee: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Harm Peter Hofstee, Ravi Nair, Steven Douglas Posluszny
  • Publication number: 20020073357
    Abstract: In one embodiment a multiprocessing apparatus includes a first processor and a second processor. Each of the processors have their own data and instruction caches to support independent operation. In a normal mode the processors independently execute separate instruction streams. Each of the processors has a respective signature generator. The system also includes a compare unit coupled to the signature generators. In a high reliability mode, both processors execute the same instruction stream. That is, each processor computes a version of a result for ones of the instructions in the stream. Responsive to the respective versions, the respective signature generators assert signatures to the compare unit, so that a faulting instruction may be detected. In another aspect, each processor has its own respective commit logic.
    Type: Application
    Filed: December 11, 2000
    Publication date: June 13, 2002
    Applicant: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Harm Peter Hofstee, Ravi Nair, Steven Douglas Posluszny