Patents by Inventor Steven Durrill

Steven Durrill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9881120
    Abstract: Various embodiments implementing a multi-fabric mixed-signal electronic system design spanning across multiple design fabrics with electrical and/or thermal analysis awareness. A schematic design may be extracted from and a power delivery network (PDN) model may be determined from a plurality of layouts in multiple design fabrics in a multi-fabric design environment platform. A PDN-aware, multi-fabric full system schematic may be constructed by assembling the PDN model and the schematic design into the PDN-aware, multi-fabric full system schematic. For a schematic generated for a circuit block of interest, chip power models may be determined for the remaining portion of the multi-fabric mixed-signal electronic system design, and the PDN-aware, multi-fabric full system schematic may be updated by accounting for the chip power models. The circuit block of interest may then be electrically and/or thermally analyzed within the context of the remaining portion.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 30, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Arnold Ginetti, Steven Durrill, Taranjit Singh Kukal
  • Patent number: 9449130
    Abstract: Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: September 20, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taranjit Singh Kukal, Steven Durrill, Utpal Bhattacharyya, Amit Sharma
  • Patent number: 9286421
    Abstract: Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: March 15, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taranjit Singh Kukal, Steven Durrill, Utpal Bhattacharyya, Amit Sharma