Abstract: An input biasing circuit for a microphone is disclosed. The circuit includes an input and an output. An input transistor is connected between the input and the output and to a biasing circuit. The biasing circuit DC biases the gate terminal of the input transistor. A resistor operably connected to, and cooperating with the input transistor, provides a buffered version of a received microphone transducer signal to the output.

Abstract: A hearing aid for converting input acoustical energy into an electrical signal, processing the signal and converting the processed electrical signal into acoustical energy is disclosed. The hearing aid includes a digitally programmable gain amplifier. The digitally programmable gain amplifier comprises circuitry for decoding a digital control input signal (referred to as the serial data input), and based upon the digital control signal it comprises a means for changing the amplifier gain.

Abstract: An impedance matching, reducing, or buffering circuit for permitting smooth signal flow from a first transmission medium to a second transmission medium. The circuit provides a first node adapted for coupling to the first transmission medium and for receiving a signal from the first transmission medium. The circuit further provides a buried channel transistor, that is coupled to the first node and that is biased by additional circuit devices, for transforming the impedance imposed on the signal. The use of the buried mode transistor reduces noise on the surface of the transistor while at the same time keeps other performance standards high. The circuit additionally provides a second node that is coupled to the buried channel transistor and that is adapted for coupling to the second transmission medium for conveying the signal to the second transmission medium.

Abstract: A buffer circuit, such as for use with a low voltage hearing aid, is disclosed. The hearing aid comprises a microphone, a receiver and an amplifier. The amplifier is disposed between the microphone and the receiver. The buffer circuit has a MOS device including a well terminal and a gate terminal equipotentially coupled together to reduce the effective threshold voltage of the MOS device, thereby reducing the gate-to-source voltage of the MOS device. This permits a greater linear output signal range for the amplifier.

Abstract: An impedance matching, reducing, or buffering circuit for permitting smooth signal flow from a first transmission medium to a second transmission medium. The circuit provides a first node adapted for coupling to the first transmission medium and for receiving a signal from the first transmission medium. The circuit further provides a buried channel transistor, that is coupled to the first node and that is biased by additional circuit devices, for transforming the impedance imposed on the signal. The use of the buried mode transistor reduces noise on the surface of the transistor while at the same time keeps other performance standards high. The circuit additionally provides a second node that is coupled to the buried channel transistor and that is adapted for coupling to the second transmission medium for conveying the signal to the second transmission medium.