Abstract: A three dimensional memory enabling both pixel and bit slice data to be stored and retrieved through different ports. A memory circuit (30) is divided into a lower memory block (32a) and an upper memory block (32b). Each memory block is organized into 256 rows .times.16 groups (pixel planes) of eight columns (bit planes). Eight bits of pixel data are stored at a selected row and pixel plane of the upper or lower memory block, and sixteen bits of pixel data are stored at a selected row and bit plane of the upper or lower memory block. Address bits determine the location of pixel data and bit slice data. A bit plane port is used to access data in the bit slice format and another port is used to access data in the pixel format. Bit slice data input through the bit plane port and stored in the memory circuit can be read as pixel data through the pixel port, and vice versa.

Abstract: The invention comprises a semiconductor substrate with a plurality of photoconductive elements. The photoconductive elements are connected to form a combinational logic ripple carry adder having only AND and OR logic gates. An optic substrate overlies the semiconductor substrate and directs light representing logic parameters onto the logic gates. The ripple carry adder has complementary inputs and complementary outputs to enable the use of only AND and OR gates.

Abstract: A reduced adder precision apparatus uses two adders to produce a serial output product of two serial input digital numbers. The multiplier operates on a bit by bit basis, beginning with the least significant bit, to determine each bit of the product without any information concerning the more significant bits. Each bit of each input is read sequentially and the bit sequences are stored in registers. A value based on the sequence built from the second digital number is added to an accumulation of a residue from a shift register used to determine the output bit of the examined bit of the first digital number is a logical one. Similarly, a value based on the sequence built from the first digital number is added to an accumulation of a residue from the shift register if the bit examined from the second digital number is a logical one.

Abstract: A multiprocessor system includes a segmentable parallel bus for dividing the multiprocessor system into several independent groups of processors. Each group of processors can access its segment of the segmentable parallel bus to carry on processing within the group simultaneously and independently of processing occurring in another group of processors on another segment of the segmentable bus. The multiprocessor system of this invention further has the capability to reconfigure the segments and processors associated therewith in order to cope with a failed processor or bus segment.