Patents by Inventor Steven E. Hossner

Steven E. Hossner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6157232
    Abstract: A local clock system for generating a local clock signal whose frequency and phase are synchronized to the frequency and phase of an external input clock reference signal, wherein the output local clock signal is a non-integer multiple of the input clock reference signal. A numerically controlled generator generates the clock output signal, and the frequency and phase thereof are controlled by a digital tuning word input thereto. An input frequency divider divides the input clock reference signal by a first constant k.sub.11 or a second constant k.sub.22, and an output frequency divider for dividing the output signal by a first constant k.sub.11 or a second constant k.sub.21. A relay-phase detector receives output signals from the input frequency divider and the output frequency divider, and produces a 0 or a 1 output, which controls the input frequency divider to divide by k.sub.12 or k.sub.22 and controls the output frequency divider to divide by k.sub.11 or k.sub.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: December 5, 2000
    Assignee: NEC Corporation
    Inventors: Steven E. Hossner, Brian F. Reilly, Jeremy H. Smith
  • Patent number: 5631928
    Abstract: An enhanced B3ZS decoder which substantially improves error-multiplication performance is disclosed. A string of four bits is examined to detect whether it satisfies two specific criteria. The first criterion is that every valid zero-substitution pattern is immediately preceded by a "one" bit. The second criterion is that successive zero-substitution BPVs are of opposite polarity. When these criteria are met, the appropriate bits are set to zero, effectively replacing the identified pattern with the original three-zero pattern.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: May 20, 1997
    Assignee: NEC America, Inc.
    Inventor: Steven E. Hossner
  • Patent number: 5337208
    Abstract: An AC current limiter, which is connected in series with a transmission line and which operates in two modes, a conductive mode and a protective mode, includes first and second transistors coupled in parallel with first and second diodes, respectively and the emitters of the first and second transistors serially coupled by a sensing element. First and second gain control networks are couple to the first and second transistors, respectively, to permit control of the gain in the first and second transistors. More particularly, as line current increases to a limiting value, the circuit operates in the protective mode. The voltage across the sensing causes a transistor in one of the first and second networks to turn on, thus diverting current from the respective first and second transistors connected in series with the transmission line. Therefore, line current is limited to a predetermined value.
    Type: Grant
    Filed: December 18, 1991
    Date of Patent: August 9, 1994
    Assignee: NEC America, Inc.
    Inventor: Steven E. Hossner
  • Patent number: 5307407
    Abstract: A low frequency high voltage AC power for a telephone system is provided by a ring signal generator, which produces a ring signal from a DC power supply using a pair of switches controlled by pulse width modulation (PWM) circuit. The ring signal generator includes a PWM circuit driving a pair of MOSFET transistors via a respective pair of opto-isolators. The output of the MOSFET transistor switches is commonly connected to a low pass filter network. The ring signal generator of the present invention advantageously produces a 65 VRMS ring signal at very high efficiency.
    Type: Grant
    Filed: December 19, 1991
    Date of Patent: April 26, 1994
    Assignee: Nec America, Inc.
    Inventors: Rolf H. G. Wendt, Steven E. Hossner