Abstract: A microelectronic structure having CTE compensation for use in wafer-level and chip-scale packages, comprising a plurality of substrate tiles each having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween.

Abstract: An apparatus comprising a first power combiner/divider network and a second power combiner/divider network. The first power combiner/divider network splits a first electromagnetic signal into split signals that are connectable to signal processor(s). The second power combiner/divider network combines processed signals into a second electromagnetic signal. The apparatus includes a three-dimensional coaxial microstructure.

Abstract: An apparatus comprising a first power combiner/divider network and a second power combiner/divider network. The first power combiner/divider network splits a first electromagnetic signal into split signals that are connectable to signal processor(s). The second power combiner/divider network combines processed signals into a second electromagnetic signal. The apparatus includes a three-dimensional coaxial microstructure.

Abstract: A microwave digital phase shifter, comprising input and output ports having a reference path and a delay path disposed in parallel therebetween, the reference path including a switch element shunted to ground and the delay path including at least one switch element shunted to ground and including a transmission line to provide a phase difference between the reference path and the delay path.

Abstract: An apparatus comprising a first power combiner/divider network and a second power combiner/divider network. The first power combiner/divider network splits a first electromagnetic signal into split signals that are connectable to signal processor(s). The second power combiner/divider network combines processed signals into a second electromagnetic signal. The apparatus includes a three-dimensional coaxial microstructure.

Abstract: An apparatus comprising a first power combiner/divider network and a second power combiner/divider network. The first power combiner/divider network splits a first electromagnetic signal into split signals that are connectable to signal processor(s). The second power combiner/divider network combines processed signals into a second electromagnetic signal. The apparatus includes a three-dimensional coaxial microstructure.

Abstract: CTE compensation for wafer-level and chip-scale packages and assemblies.

Abstract: An apparatus comprising a first power combiner/divider network and a second power combiner/divider network. The first power combiner/divider network splits a first electromagnetic signal into split signals that are connectable to signal processor(s). The second power combiner/divider network combines processed signals into a second electromagnetic signal. The apparatus includes a three-dimensional coaxial microstructure.

Abstract: An apparatus comprising a first power combiner/divider network and a second power combiner/divider network. The first power combiner/divider network splits a first electromagnetic signal into split signals that are connectable to signal processor(s). The second power combiner/divider network combines processed signals into a second electromagnetic signal. The apparatus includes a three-dimensional coaxial microstructure.

Abstract: An apparatus comprising a first power combiner/divider network and a second power combiner/divider network. The first power combiner/divider network splits a first electromagnetic signal into split signals that are connectable to signal processor(s). The second power combiner/divider network combines processed signals into a second electromagnetic signal. The apparatus includes a three-dimensional coaxial microstructure.

Abstract: An apparatus comprising a first power combiner/divider network and a second power combiner/divider network. The first power combiner/divider network splits a first electromagnetic signal into split signals that are connectable to signal processor(s). The second power combiner/divider network combines processed signals into a second electromagnetic signal. The apparatus includes a three-dimensional coaxial microstructure.

Abstract: A power-combined amplifier and method are provided. In one aspect, the power-combined amplifier and method overcome problems associated with decreased output power efficiency caused by phase mismatch between constituent amplifiers.

Abstract: An apparatus comprising a first power combiner/divider network and a second power combiner/divider network. The first power combiner/divider network splits a first electromagnetic signal into split signals that are connectable to signal processor(s). The second power combiner/divider network combines processed signals into a second electromagnetic signal. The apparatus includes a three-dimensional coaxial microstructure.

Abstract: An N-way multi-layer radial power combiner/divider comprises an RF layer including N planar RF transmission lines radiating from a common port to N ports. An isolation layer substantially parallel to the RF layer comprises a star resistor having N resistive arms radiating from a common junction and N planar isolation transmission lines coupled in series to respective resistive arms. Each series pair of a resistive arm and an isolation transmission line is ideally a half-wavelength in electrical length. N vertical interconnects between the RF layer and the isolation layer connect the ends of the N isolation transmission lines to the ends of the N RF transmission lines at the N individual ports, respectively. Any path from one individual port through the common junction of the star resistor to another individual port is approximately a full wavelength ?c or multiple thereof so that the phase angle through the isolation network is approximately zero degrees.

Abstract: An N-way multi-layer radial power combiner/divider comprises an RF layer including N planar RF transmission lines radiating from a common port to N ports. An isolation layer substantially parallel to the RF layer comprises a star resistor having N resistive arms radiating from a common junction and N planar isolation transmission lines coupled in series to respective resistive arms. Each series pair of a resistive arm and an isolation transmission line is ideally a half-wavelength in electrical length. N vertical interconnects between the RF layer and the isolation layer connect the ends of the N isolation transmission lines to the ends of the N RF transmission lines at the N individual ports, respectively. Any path from one individual port through the common junction of the star resistor to another individual port is approximately a full wavelength ?c or multiple thereof so that the phase angle through the isolation network is approximately zero degrees.

Abstract: A multiple terminal selector switch for use with millimeter-wave signals has a layout of components enabling the switch to be constructed on a monolithic microwave integrated circuit (MMIC) chip while maintaining adequately low cross talk among ports of the switch to retain isolation among its ports. The circuitry includes a transmission line having multiple taps spaced apart by an integral number of half wavelengths of the signal, wherein the taps connect to separate ports via arms of the circuit. Each arm has an electronically switchable element for producing open or short circuits for connection and disconnection of a switch port from the transmission line. One primary tap of the transmission line is unswitched and connects with a further port from which, or to which, signals of the other ports are selectively switched.

Abstract: A voltage variable attenuator is described including a quadrature hybrid coupler having an input port, an output port, a first reflective port and a second reflective port. The voltage variable attenuator further includes a first and a second impedance network, the first impedance network connected to the first reflective port of the quadrature hybrid coupler, the second impedance network connected to the second reflective port of the quadrature hybrid coupler, each impedance network including a first RF propagation network having a first end connected to the respective reflective port of the quadrature hybrid coupler. Each impedance network further includes a second end of the first RF propagation network connected to a field effect transistor having a drain electrode, a source electrode and a gate electrode, the drain electrode connected to the second end of the first RF propagation network.