Abstract: An electronic device display may have pixels formed from crystalline semiconductor light-emitting diode dies, organic light-emitting diodes, or other pixel structures. The pixels may be formed on a display panel substrate. A display panel may extend continuously across the display or multiple display panels may be tiled in two dimensions to cover a larger display area. Interconnect substrates may have outwardly facing contacts that are electrically shorted to corresponding inwardly facing contacts such as inwardly facing metal pillars associated with the display panels. The interconnect substrates may be supported by glass layers. Integrated circuits may be embedded in the display panels and/or in the interconnect substrates. A display may have an active area with pixels that includes non-spline pixels in a non-spline display portion located above a straight edge of the display and spline pixel in a spline display portion located above a curved edge of the display.

Abstract: Systems, methods, and software for filtering components, such as hardware components, compatible with computer-modeled structures are presented. A compatible components system provides selection methods that present components compatible with computer-aided design (CAD) models designed in computer modeling software. The system executes methods designed to filter components made available to designers using attribute information of the features and attribute information of the components. Designers may interact with the compatibility methods numerous times, narrowing components through a series or number of filtering steps until a desired compatible component is easily selected. The computer modeling software may include graphical user interfaces for selecting component source locations, filtering types of components presented by the system, and adding components to CAD models.

Abstract: Systems, methods, and software for filtering components, such as hardware components, compatible with computer-modeled structures are presented. A compatible components system provides selection methods that present components compatible with computer-aided design (CAD) models designed in computer modeling software. The system executes methods designed to filter components made available to designers using attribute information of the features and attribute information of the components. Designers may interact with the compatibility methods numerous times, narrowing components through a series or number of filtering steps until a desired compatible component is easily selected. The computer modeling software may include graphical user interfaces for selecting component source locations, filtering types of components presented by the system, and adding components to CAD models.

Abstract: A power wedge device includes a base, a screw-type cone wedge mounted to the base and including a threaded cone portion that tapers to a pointed tip. A motor is mounted to the base and coupled to the screw-type cone wedge to rotatably drive the threaded cone portion. A counter-rotational member is coupled to the base and is configured to ground the screw-type cone wedge so as to prevent the screw-type cone wedge from spinning the motor and the base.

Abstract: A power wedge device includes a base, a screw-type cone wedge mounted to the base and including a threaded cone portion that tapers to a pointed tip. A motor is mounted to the base and coupled to the screw-type cone wedge to rotatably drive the threaded cone portion. A counter-rotational member is coupled to the base and is configured to ground the screw-type cone wedge so as to prevent the screw-type cone wedge from spinning the motor and the base.

Abstract: A network node destination module for ensuring proper reception and transmission of information over a network having an optional network reference clock including an input stage for receiving the information, a synchronous residual time stamp (SRTS) timing control stage for implementing digital phase comparison techniques utilizing the network reference clock, and a clock generation stage for generating a transmit clock in response to a control value generated by the SRTS timing control stage. The SRTS timing control stage maintains a constant phase offset between the receive clock of the source node and the transmit clock of the destination node. The SRTS timing control stage includes an RTS sample generator for generating a local RTS sample for comparison with the source RTS sample to determine a current phase offset between the source and clocks. The current phase offset is then compared to a target phase offset stored in a phase register to generate a control value.

Abstract: A network node destination module for ensuring proper reception and transmission of information over a network having an optional network reference clock including an input stage for receiving the information, a synchronous residual time stamp (SRTS) timing control stage for implementing digital phase comparison techniques utilizing the network reference clock, and a clock generation stage for generating a transmit clock in response to a control value generated by the SRTS timing control stage. The SRTS timing control stage maintains a constant phase offset between the receive clock of the source node and the transmit clock of the destination node. The SRTS timing control stage includes an RTS sample generator for generating a local RTS sample for comparison with the source RTS sample to determine a current phase offset between the source and clocks. The current phase offset is then compared to a target phase offset stored in a phase register to generate a control value.

Abstract: An improved SRTS clock recovery system of a network node comprising a novel adaptifier arrangement that continually monitors the flow of data through a data FIFO and briefly assumes control over the SRTS clock recovery system to permanently adjust the phase and/or temporarily adjust the frequency of a transmit clock to avoid dataflow errors. Specifically, the adaptifier includes a phase controller that permanently adjusts a target phase offset utilized by the SRTS clock recovery system to effect a permanent change in the transmit clock phase. A frequency controller of the adaptifier temporarily overrides an error signal generated by the SRTS clock recovery system prior to it being utilized by a clock generator to effect a temporary adjustment of the transmit clock frequency. Clock perturbations are minimized, including graceful entry and exit of adaptifier action. The adaptifier implements either or both adjustments to avoid an impending dataflow error based upon a number of predetermined conditions.