Abstract: In various embodiments, a tissue thickness compensator can comprise one or more capsules and/or pockets comprising at least one medicament therein. In at least one embodiment, staples can be fired through the tissue thickness compensator to rupture the capsules. In certain embodiments, a firing member, or knife, can be advanced through the tissue thickness compensator to rupture the capsules.

Abstract: An automated system and method for classifying audio or audio/video signals as music or non-music is provided. A spectrum module receives at least one digitized audio signal from a source and generates representations of the power distribution of the audio signal with respect to frequency and time. A first moment module calculates, for each time instant, a first moment of the distribution representation with respect to frequency and in turn generates a representation of a time series of first moment values.A degree of variation module in turn calculates a measure of degree of variation with respect to time of the values of the time series and produces a representation of the first moment time series variation measuring values.

Abstract: A central processing unit (CPU) 10 comprises an external control memory for storing microinstructions which correspond to macroinstructions read from a system memory. The microinstructions are 56 bits in length and are read in 28-bit segments. CPU 10 also comprises an internal memory management unit (MMU) 18 which comprises a plurality of address translation entry (ATE) registers four of which are permanent and sixteen of which are temporary in that the storage of a new translation entry occurs in a least recently used temporary translation entry register. CPU 10 also comprises a plurality of status register bits, some of which are settable only by predefined microinstructions. All of the status register bits are branchable. CPU 10 further comprises a condition code register the state of which may be determined by input signal pins. CPU 10 also comprises address generation logic which may generate a 24, 31 or 32 bit address upon a 32-bit address bus.