Abstract: A technique for selecting an optimal quantization direction for a given transport direction in a semiconductor device such as a field effect transistor (FET), a method for preparing a wafer for fabricating such a semiconductor device, and the semiconductor device fabricated by the method. A switching time is calculated for different candidate quantization directions, and for a given current transport direction. The quantization direction that results in the lowest switching time is then determined. In a specific example, Ge nFET performance is enhanced by 12% using the [1 1 0] and [{overscore (4)} 4 21] crystallographic directions for transport and quantization, respectively. Quantization in the [{overscore (1)} 1 0] direction was previously considered optimal.

Abstract: A method (and structure) for an electronic chip having at least one layer of material for which a carrier mobility of a first carrier type is higher in a first crystal surface than in a second crystal surface and for which a carrier mobility of a second carrier type is higher in the second crystal surface than the first crystal surface includes a first device having at least one component fabricated on the first crystal surface of the material, wherein an activity of the component of the first device involves primarily the first carrier type, and a second device having at least one component fabricated on the second crystal surface of the material, wherein an activity of the component of the second device involves primarily the second carrier type.

Abstract: A method (and structure) for an electronic chip having at least one layer of material for which a carrier mobility of a first carrier type is higher in a first crystal surface than in a second crystal surface and for which a carrier mobility of a second carrier type is higher in the second crystal surface than the first crystal surface includes a first device having at least one component fabricated on the first crystal surface of the material, wherein an activity of the component of the first device involves primarily the first carrier type, and a second device having at least one component fabricated on the second crystal surface of the material, wherein an activity of the component of the second device involves primarily the second carrier type.

Abstract: An electrical device which employs two-dimensional space charge modulation in a semiconductor structure. The device has an approximately Debye length wide contact and a rectifying contact positioned adjacent to each other within a Debye length on a semiconductor body and a contact remotely positioned. A bias on the rectifying contact will effect conduction between the other contacts.