Abstract: An inter-processor data transfer management system uses an interface circuit to decouple a requesting processor from a responding processor so that the requesting processor does not need to wait for the responding processor after transmitting a data transfer request. The data transfer request is stored in an interface circuit between the processors. The interface circuit arbitrates for the responding processor bus, and completes the data transfer when granted access by the responding processor. For read sequences the requesting processor receives a data word from the interface circuit as the data transfer request is stored in the interface circuit. The first data word received by the requesting processor during a read operation is ignored, and the last data transfer request during a read operation has a dummy address.