Abstract: A closed-loop switch-mode boost converter includes a switching signal generator circuit, a switch-mode boost amplifier, a filter circuit, and an error amplifier circuit. The switching signal generator circuit receives an input signal and outputs a switching signal. A duty-cycle of the switching signal has a first non-linear relationship to an amplitude of the input signal. The switch-mode boost amplifier receives the switching signal and produces an output signal. An amplitude of the output signal has a second non-linear relationship to the duty-cycle of the switching signal, and the output signal has a linear relationship to the input signal based on the first and second non-linear relationships. The filter circuit receives the output signal and outputs a filtered output signal. The error amplifier circuit receives the input signal and the filtered output signal and produces a feedback control signal. The filtered output signal is adjusted based on the feedback control signal.

Abstract: A charge pump having only NMOS devices charges a plurality of capacitors to a parallel charged voltage level by electrically connecting the capacitors in parallel between an input voltage node and a ground by activating a plurality of first NMOS transistor switches and a plurality of second NMOS transistor switches and deactivating a plurality of third NMOS transistor switches. The charge pump then generates a series capacitor output voltage level at a capacitor series output node by electrically connecting and discharging the capacitors in series between the input voltage node and the capacitor series output node by activating the third NMOS transistor switches and deactivating the first NMOS transistor switches and the second NMOS transistor switches.

Abstract: A pulsed laser diode driver includes an inductor having a first terminal configured to receive a source voltage. A source capacitor has a first terminal connected to the first terminal of the inductor to provide the source voltage. A bypass switch has a drain node connected to a second terminal of the inductor and to a first terminal of a bypass capacitor. A laser diode has an anode connected to the second terminal of the inductor and to the drain node of the bypass switch. A laser diode switch has a drain node connected to a cathode of the laser diode. The laser diode switch and the bypass switch control a current flow through the inductor to produce a high-current pulse through the laser diode, the high-current pulse corresponding to a peak current of a resonant waveform developed at the anode of the laser diode.

Abstract: A width of a voltage pulse signal is directly proportional to a difference between first and second resistances in a pulse generator. The voltage pulse signal is generated with a ramp signal, two reference voltages, and two comparators. The first reference voltage is generated with the first resistance and a first current, and the second reference voltage is generated with the second resistance and a second current. The first comparator produces a first comparator output in response to the first reference voltage and the ramp signal, and the second comparator produces a second comparator output in response to the second reference voltage and the ramp signal. A logic circuitry generates the voltage pulse signal in response to the two comparator outputs.

Abstract: A charge pump having only NMOS devices charges a plurality of capacitors to a parallel charged voltage level by electrically connecting the capacitors in parallel between an input voltage node and a ground by activating a plurality of first NMOS transistor switches and a plurality of second NMOS transistor switches and deactivating a plurality of third NMOS transistor switches. The charge pump then generates a series capacitor output voltage level at a capacitor series output node by electrically connecting and discharging the capacitors in series between the input voltage node and the capacitor series output node by activating the third NMOS transistor switches and deactivating the first NMOS transistor switches and the second NMOS transistor switches.

Abstract: An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.

Abstract: A width of a voltage pulse signal is directly proportional to a difference between first and second resistances in a pulse generator. The voltage pulse signal is generated with a ramp signal, two reference voltages, and two comparators. The first reference voltage is generated with the first resistance and a first current, and the second reference voltage is generated with the second resistance and a second current. The first comparator produces a first comparator output in response to the first reference voltage and the ramp signal, and the second comparator produces a second comparator output in response to the second reference voltage and the ramp signal. A logic circuitry generates the voltage pulse signal in response to the two comparator outputs.

Abstract: An improved circuit or method generates first and second initial pulses that do not overlap. First and second drive pulses are generated based on the first and second initial pulses, respectively. A first transistor is turned on with the first drive pulses. A second transistor is turned on with the second drive pulses. A current flows in response to an on-time state of the first transistor overlapping with an on-time state of the second transistor. A delay of the second drive pulses is decreased based on a time of the current flow overlapping with one of the first initial pulses; and the delay of the second drive pulses is increased based on the time of the current flow overlapping with one of the second initial pulses.

Abstract: An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.

Abstract: A charge pump having only NMOS devices charges a plurality of capacitors to a parallel charged voltage level by electrically connecting the capacitors in parallel between an input voltage node and a ground by activating a plurality of first NMOS transistor switches and a plurality of second NMOS transistor switches and deactivating a plurality of third NMOS transistor switches. The charge pump then generates a series capacitor output voltage level at a capacitor series output node by electrically connecting and discharging the capacitors in series between the input voltage node and the capacitor series output node by activating the third NMOS transistor switches and deactivating the first NMOS transistor switches and the second NMOS transistor switches.

Abstract: An improved circuit or method generates first and second initial pulses that do not overlap. First and second drive pulses are generated based on the first and second initial pulses, respectively. A first transistor is turned on with the first drive pulses. A second transistor is turned on with the second drive pulses. A current flows in response to an on-time state of the first transistor overlapping with an on-time state of the second transistor. A delay of the second drive pulses is decreased based on a time of the current flow overlapping with one of the first initial pulses; and the delay of the second drive pulses is increased based on the time of the current flow overlapping with one of the second initial pulses.

Abstract: An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.

Abstract: A width of a voltage pulse signal is directly proportional to a difference between first and second resistances in a pulse generator. The voltage pulse signal is generated with a ramp signal, two reference voltages, and two comparators. The first reference voltage is generated with the first resistance and a first current, and the second reference voltage is generated with the second resistance and a second current. The first comparator produces a first comparator output in response to the first reference voltage and the ramp signal, and the second comparator produces a second comparator output in response to the second reference voltage and the ramp signal. A logic circuitry generates the voltage pulse signal in response to the two comparator outputs.

Abstract: A charge pump having only NMOS devices charges a plurality of capacitors to a parallel charged voltage level by electrically connecting the capacitors in parallel between an input voltage node and a ground by activating a plurality of first NMOS transistor switches and a plurality of second NMOS transistor switches and deactivating a plurality of third NMOS transistor switches. The charge pump then generates a series capacitor output voltage level at a capacitor series output node by electrically connecting and discharging the capacitors in series between the input voltage node and the capacitor series output node by activating the third NMOS transistor switches and deactivating the first NMOS transistor switches and the second NMOS transistor switches.

Abstract: An open-loop switch-mode boost converter includes a switching signal generator circuit that receives a time-varying input signal and outputs a switching signal. A duty-cycle of the switching signal has a first non-linear relationship to an amplitude of the time-varying input signal. An amplifier receives the switching signal and outputs a time-varying output signal, an amplitude of which has a second non-linear relationship to the duty-cycle of the switching signal. The time-varying output signal has a linear relationship to the time-varying input signal based on the first non-linear relationship and the second non-linear relationship. A filter circuit receives the time-varying output signal and outputs a filtered time-varying output signal which has a maximum frequency component that is substantially the same as a maximum frequency component of the time-varying input signal. The switching signal generator circuit is communicatively isolated from the voltage output node and the filter output node.

Abstract: A method is described for measuring the noise parameters of field effect transistors (FETs) while still in the wafer stage. Instead of conducting lengthy testing of each individual device at the operating frequency of interest after the devices have been diced, mounted and bonded, each of the devices on a wafer is automatically probed to obtain the standard S-parameters and also the FET's output noise power P.sub.n at a frequency at which parasitic probe effects are avoided. The various noise parameters can then be calculated for higher operating frequencies of interest from FET equivalent circuit parameters derived from the S-parameters, and from P.sub.n, either before or after dicing.