Abstract: A router for interconnecting N interfacing peripheral devices. The router comprises routing nodes coupled to one another via switching circuitry. A first routing nodes comprises: 1) a physical medium device (PMD) module for transmitting data packets to and receiving data packets from the N interfacing peripheral devices; 2) an ingress processor for receiving incoming data packets from the PMD module; 3) an egress processor for transmitting data packets to the PMD module; and 4) a medium access control (MAC) processor for forwarding data packets from the ingress processor to the switching circuitry and forwarding data packets from the switching circuitry to the egress processor. The MAC processor determines whether a first data packet received from the ingress processor is directed to the egress processor and, if so, transfers the first data packet directly to the egress processor without forwarding the first data packet through the switching circuitry.

Abstract: A system and method is disclosed for synchronizing a plurality of processors in a processor array. The system and method synchronizes data communications between the processors by regulating memory access of the processors to memory bytes of an asynchronous variable memory. Each memory byte in the asynchronous variable memory is a “read full and write empty” memory byte. Except for a system processor, each processor in the process array can only write data to an empty memory byte and can only read data from a full memory byte. The processors are prevented from untimely overwriting data and from untimely reading data. This keeps the data communications between the processors properly synchronized.

Abstract: A system and method is disclosed for synchronizing a plurality of processors in a processor array. The system and method synchronizes data communications between the processors by regulating memory access of the processors to memory bytes of an asynchronous variable memory. Each memory byte in the asynchronous variable memory is a “read full and write empty” memory byte. Except for a system processor, each processor in the process array can only write data to an empty memory byte and can only read data from a full memory byte. The processors are prevented from untimely overwriting data and from untimely reading data. This keeps the data communications between the processors properly synchronized.