Abstract: Embodiments included herein are directed towards a fractional feedback divider circuit and associated method. The circuit may include a programmable feedback divider including a plurality of flip-flops arranged in series. The programmable feedback divider may be configured to receive an input clock signal and a reset signal comprising at least one pulse and to generate a divided clock. The circuit may include reset logic configured to receive an input from the programmable feedback divider and to generate a reset signal. The circuit may include a first D flip-flop configured to receive the reset signal and to generate an output and a second D flip-flop configured to receive the output from the first D flip-flop and to generate a second output. The circuit may further include a multiplexer configured to receive the second output and to generate an output clock signal.

Abstract: A circuit can include a non-inverter circuit configured to generate a first clock signal with a first logic state during a first period of time in response to an input clock signal having the first logic state, and with a second logic state during a second period of time in response to the input clock signal having the second logic state. The circuit can include an inverter circuit that can be configured to generate a second clock signal with the second logic state during the first period of time in response to the input clock signal having the first logic state, and with the second logic state during the second period of time in response to the input clock signal having the second logic state.