Abstract: In an embodiment, an apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.

Abstract: An apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.

Abstract: In an embodiment, an apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.

Abstract: In an embodiment, an apparatus is disclosed that comprises a voltage regulator and a regulator booster. The voltage regulator is supplied by an input and is configured to generate a regulated output. The regulated output has a voltage corresponding to an operating point of the voltage regulator. The regulator booster is connected to the voltage regulator and, when activated, is configured to boost the voltage of the regulated output by a target amount. The target amount is at least a portion of a magnitude of a voltage droop relative to the operating point that is caused by a change in a current load on the regulated output.

Abstract: An apparatus includes a first half-cell, a second half-cell, a multiplexer and a decision feedback equalizer. The first input stage may be configured to present a first differential input to the first auto-zero stage and the second auto-zero stage. The second input stage may be configured to present a second differential input to the third auto-zero stage and the fourth auto-zero stage. The multiplexer may be configured to receive a first output from the first auto-zero stage, receive a second output from the third auto-zero stage and present a decision feedback input comprising one of the first output and the second output. The decision feedback equalizer may be configured to generate a feedback signal in response to the decision feedback input and present the feedback signal to the first feedback buffer and the second feedback buffer.

Abstract: An apparatus includes a first half-cell, a second half-cell, a multiplexer and a decision feedback equalizer. The first input stage may be configured to present a first differential input to the first auto-zero stage and the second auto-zero stage. The second input stage may be configured to present a second differential input to the third auto-zero stage and the fourth auto-zero stage. The multiplexer may be configured to receive a first output from the first auto-zero stage, receive a second output from the third auto-zero stage and present a decision feedback input comprising one of the first output and the second output. The decision feedback equalizer may be configured to generate a feedback signal in response to the decision feedback input and present the feedback signal to the first feedback buffer and the second feedback buffer.

Abstract: A circuit includes a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a first input control signal, and the first current terminal coupled to a first power supply node. The circuit also includes a first resistor coupled to the first control input of the first transistor, a first capacitor coupled between the second current terminal of the first transistor and the first resistor and a second transistor comprising a second control input and third and fourth current terminals, the third current terminal coupled to the first resistor and to the first capacitor.

Abstract: A semiconductor die. The die comprises a level shifter coupled to a positive differential input and to a negative differential input comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage coupled to a positive differential output and to a negative differential output, a positive alternating current (AC) coupled feed-forward path comprising a first capacitor coupled to the positive differential input and to the positive differential output, a negative AC coupled feed-forward path comprising a second capacitor coupled to the negative differential input and to the negative differential output, a positive direct current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output, and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.

Abstract: An apparatus includes a plurality of coarse delay circuits and a phase blender circuit. The coarse delay circuits may be configured to (i) receive an input clock signal, (ii) receive a plurality of control signals and (iii) generate a first phase signal and a second phase signal. The phase blender circuit may be configured to (i) receive the first phase signal and the second phase signal, (ii) receive a phase control signal, (iii) step between stages implemented by the coarse delay circuits and (iv) present an output clock signal. The phase blender circuit may mitigate a mismatch between the stages of the coarse delay circuits by interpolating an amount of coarse delay provided by the coarse delay circuits.

Abstract: A circuit includes a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a first input control signal, and the first current terminal coupled to a first power supply node. The circuit also includes a first resistor coupled to the first control input of the first transistor, a first capacitor coupled between the second current terminal of the first transistor and the first resistor and a second transistor comprising a second control input and third and fourth current terminals, the third current terminal coupled to the first resistor and to the first capacitor.

Abstract: An apparatus includes a plurality of coarse delay circuits and a phase blender circuit. The coarse delay circuits may be configured to (i) receive an input clock signal, (ii) receive a plurality of control signals and (iii) generate a first phase signal and a second phase signal. The phase blender circuit may be configured to (i) receive the first phase signal and the second phase signal, (ii) receive a phase control signal, (iii) step between stages implemented by the coarse delay circuits and (iv) present an output clock signal. The phase blender circuit may mitigate a mismatch between the stages of the coarse delay circuits by interpolating an amount of coarse delay provided by the coarse delay circuits.

Abstract: A semiconductor die. The die comprises a level shifter coupled to a positive differential input and to a negative differential input comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage coupled to a positive differential output and to a negative differential output, a positive alternating current (AC) coupled feed-forward path comprising a first capacitor coupled to the positive differential input and to the positive differential output, a negative AC coupled feed-forward path comprising a second capacitor coupled to the negative differential input and to the negative differential output, a positive direct current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output, and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.

Abstract: A semiconductor die. The die comprises a level shifter coupled to a positive differential input and to a negative differential input comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage coupled to a positive differential output and to a negative differential output, a positive alternating current (AC) coupled feed-forward path comprising a first capacitor coupled to the positive differential input and to the positive differential output, a negative AC coupled feed-forward path comprising a second capacitor coupled to the negative differential input and to the negative differential output, a positive direct current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output, and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.

Abstract: A circuit includes a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a first input control signal, and the first current terminal coupled to a first power supply node. The circuit also includes a first resistor coupled to the first control input of the first transistor, a first capacitor coupled between the second current terminal of the first transistor and the first resistor and a second transistor comprising a second control input and third and fourth current terminals, the third current terminal coupled to the first resistor and to the first capacitor.

Abstract: A semiconductor die. The die comprises a level shifter coupled to a positive differential input and to a negative differential input comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage coupled to a positive differential output and to a negative differential output, a positive alternating current (AC) coupled feed-forward path comprising a first capacitor coupled to the positive differential input and to the positive differential output, a negative AC coupled feed-forward path comprising a second capacitor coupled to the negative differential input and to the negative differential output, a positive direct current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output, and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.

Abstract: A driver circuit includes a first termination resistor and a distributed amplifier comprising a plurality of pairs of input transistors and comprising inductors coupled between each pair of input transistors. The driver circuit also includes a distributed current-mode level shifter coupled to the first termination resistor. The distributed current-mode level shifter includes a first plurality of inductors coupled in series between the first termination resistor and the distributed amplifier and a first plurality of capacitive devices. Each capacitive device is coupled to a power supply node and to a node interconnecting two of the series-coupled inductors.

Abstract: A driver circuit includes a first termination resistor and a distributed amplifier comprising a plurality of pairs of input transistors and comprising inductors coupled between each pair of input transistors. The driver circuit also includes a distributed current-mode level shifter coupled to the first termination resistor. The distributed current-mode level shifter includes a first plurality of inductors coupled in series between the first termination resistor and the distributed amplifier and a first plurality of capacitive devices. Each capacitive device is coupled to a power supply node and to a node interconnecting two of the series-coupled inductors.

Abstract: A loop filter with an active discrete-level loop filter capacitor can be used in a VCO (such as for CDR). A loop filter capacitor function is simulated by sensing input loop filter current (such as with a current mirror and source follower in the input leg), and forcing back a loop filter (VCO) control voltage. Loop filter voltage control is provided using a VDAC with a discrete-level VDAC feedback voltage, incremented/decremented based on the sensed loop filter current. In one embodiment, the VDAC voltage is provided as the non-inverting input to an amplifier, with the inverting input providing the control voltage, forced to the VDAC feedback voltage. The VDAC feedback voltage can be provided by increment/decrement comparators based on a voltage deviation on a C2 capacitor (from a reference voltage) that receives the sensed loop filter current (effectively multiplying the C2 capacitance to provide a simulated loop filter capacitance).

Abstract: A loop filter with an active discrete-level loop filter capacitor can be used in a VCO (such as for CDR). A loop filter capacitor function is simulated by sensing input loop filter current (such as with a current mirror and source follower in the input leg), and forcing back a loop filter (VCO) control voltage. Loop filter voltage control is provided using a VDAC with a discrete-level VDAC feedback voltage, incremented/decremented based on the sensed loop filter current. In one embodiment, the VDAC voltage is provided as the non-inverting input to an amplifier, with the inverting input providing the control voltage, forced to the VDAC feedback voltage. The VDAC feedback voltage can be provided by increment/decrement comparators based on a voltage deviation on a C2 capacitor (from a reference voltage) that receives the sensed loop filter current (effectively multiplying the C2 capacitance to provide a simulated loop filter capacitance).