Abstract: Coupled noise from at least one out-of-context aggressor net of an integrated circuit design is computed for an out-of-context victim net. The nets are out-of-context with respect to a hierarchical noise analysis of the integrated circuit design. At least one of the nets is a continuation of a path which extends to at least one in-context portion of the integrated circuit design. An aggressor signal timing window is derived for the at least one out-of-context aggressor net; a victim signal timing window is derived for the out-of-context victim net; and a timing window and noise analysis is completed with the aggressor signal timing window and the victim signal timing window. The aggressor window is derived as a function of required arrival time of the at least one out-of-context aggressor net and/or the victim window is derived as a function of required arrival time of the out-of-context victim net.

Abstract: An EQUATE property is introduced into the layout cell data for a layout design to identify the schematic to which the layout design corresponds. Rather than exploding the layout cell up to the next level for flat checking because the equivalent schematic is not known, the layout cell instances may then be checked hierarchically, with one instance checked internally for compliance with design rules and the like while the remaining instances are merely checked for proper connection to neighboring cells. New layout cell designs may therefore be created as the need arises during layout without requiring schematic checking tools to be rerun.