Patents by Inventor Steven F. HOOVER

Steven F. HOOVER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12265767
    Abstract: A system and method allows resimulation of a portion of a model of an electronic circuit. The system and model may predict and cache data associated with the resimulation of the portion (e.g., the initial state and input signals associated with the portion) in a computer memory. If a request is received to resimulation the portion, the system and method may use the cached data to perform the resimulation.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: April 1, 2025
    Inventor: Steven F. Hoover
  • Publication number: 20230059335
    Abstract: A system and method transforms a model of electronic circuit to improve emulation speed and/or reduce emulation area. The model may be divided into partitions; a sequence of storage elements may be created on a partition boundary to allow a partition to process the contents of the storage elements. The disposition of the sequence may correspond to a connection between hardware emulation elements to compensate for latencies therebetween.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 23, 2023
    Inventor: Steven F. Hoover
  • Publication number: 20230060111
    Abstract: A system and method transforms a model of electronic circuit to improve simulation speed and/or reduce emulation area. The model may include storage elements; one or more of these storage elements may be represented by dense memory, and the storage elements may be represented by references thereto.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 23, 2023
    Inventor: Steven F. Hoover
  • Publication number: 20230054303
    Abstract: A system and method allows resimulation of a portion of a model of an electronic circuit. The system and model may predict and cache data associated with the resimulation of the portion (e.g., the initial state and input signals associated with the portion) in a computer memory. If a request is received to resimulation the portion, the system and method may use the cached data to perform the resimulation.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 23, 2023
    Inventor: Steven F. Hoover
  • Patent number: 11501475
    Abstract: A system displays a visual representation of the operation of an electronic circuit. The position of graphical elements representing values of signals in the circuit convey information about the operation of the circuit. The visual representation may further depict navigable levels of hierarchy of the electronic circuit.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: November 15, 2022
    Inventor: Steven F. Hoover
  • Publication number: 20210375014
    Abstract: A system displays a visual representation of the operation of an electronic circuit. The position of graphical elements representing values of signals in the circuit convey information about the operation of the circuit. The visual representation may further depict navigable levels of hierarchy of the electronic circuit.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 2, 2021
    Inventor: Steven F. Hoover
  • Patent number: 10454850
    Abstract: Apparatuses, methods and storage medium associated with buffering data in a switch are provided. In embodiments, the switch may include a plurality of queue buffers, a plurality of queues respectively associated with the plurality of queue buffers, a shared buffer, and a queue point controller coupled with the plurality of queue buffers and the shared buffer. In embodiments the queue point controller may be configured to determine an amount of available space in a selected queue buffer of the plurality of queue buffers. The queue point controller may be further configured to allocate at least a portion of the shared buffer to a selected queue that is associated with the selected queue buffer. In embodiments, this allocation may be based on the amount of available space determined in the selected queue buffer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Albert S. Cheng, Thomas D. Lovett, Michael S. Parker, Steven F. Hoover
  • Patent number: 10326711
    Abstract: Apparatuses, methods and storage media associated with multiple multi-drop buses in a switch are provided herein. In some embodiments, the switch may include a multi-drop row bus to transmit a plurality of frames in a row dimension of the matrix switch and a multi-drop column bus to transmit the plurality of frames in a column dimension of the matrix switch. The switch may further include an input port to receive the plurality of frames and an output port to output the plurality of frames from the matrix switch. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Albert S. Cheng, Thomas D. Lovett, Michael A. Parker, Steven F. Hoover, Gregory J. Hubbard
  • Publication number: 20180287953
    Abstract: Apparatuses, methods and storage medium associated with the placement of data packets in one or more queues of a switch are described herein. In embodiments, the switch may include a plurality of virtual lane (VL) queues (VLQs) and a plurality of generic queues (GQs). A queue manager may be configured to selectively place a packet of a particular VL in a corresponding VLQ or a GQ. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 23, 2014
    Publication date: October 4, 2018
    Inventors: Albert S. CHENG, Michael A. PARKER, Thomas D. LOVETT, Steven F. HOOVER
  • Publication number: 20180287963
    Abstract: Apparatuses, methods and storage media associated with multiple multi-drop buses in a switch are provided herein. In some embodiments, the switch may include a multi-drop row bus to transmit a plurality of frames in a row dimension of the matrix switch and a multi-drop column bus to transmit the plurality of frames in a column dimension of the matrix switch. The switch may further include an input port to receive the plurality of frames and an output port to output the plurality of frames from the matrix switch. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 24, 2014
    Publication date: October 4, 2018
    Inventors: Albert S. CHENG, Thomas D. LOVETT, Michael A. PARKER, Steven F. HOOVER, Gregory J. HUBBARD
  • Publication number: 20170295112
    Abstract: Apparatuses, methods and storage medium associated with buffering data in a switch are provided. In embodiments, the switch may include a plurality of queue buffers, a plurality of queues respectively associated with the plurality of queue buffers, a shared buffer, and a queue point controller coupled with the plurality of queue buffers and the shared buffer. In embodiments the queue point controller may be configured to determine an amount of available space in a selected queue buffer of the plurality of queue buffers. The queue point controller may be further configured to allocate at least a portion of the shared buffer to a selected queue that is associated with the selected queue buffer. In embodiments, this allocation may be based on the amount of available space determined in the selected queue buffer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 24, 2014
    Publication date: October 12, 2017
    Inventors: Albert S. CHENG, Thomas D. LOVETT, Michael S. PARKER, Steven F. HOOVER