Patents by Inventor Steven F. Oakland
Steven F. Oakland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9599664Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.Type: GrantFiled: May 15, 2015Date of Patent: March 21, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Luke D. Lacroix, Mark C. H. Lamorey, Steven F. Oakland, Janak G. Patel, Kerry P. Pfarr, Peter Slota, Jr., David B. Stone
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Patent number: 9172373Abstract: Structures, methods, and systems for designing and verifying integrated circuits including redundant logic blocks are provided. An integrated circuit includes selection logic and selectable logic blocks that are individually controllable by the selection logic. The selectable logic blocks include respective instances of a redundant logic block, and respective instances of an interface logic block that selectively disable the redundant logic blocks in the integrated circuit.Type: GrantFiled: September 6, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Kevin W. Gorman, Steven F. Oakland, Michael R. Ouellette, Steven J. Urish
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Publication number: 20150247896Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.Type: ApplicationFiled: May 15, 2015Publication date: September 3, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luke D. Lacroix, Mark C. H. Lamorey, Steven F. Oakland, Janak G. Patel, Kerry P. Pfarr, Peter Slota, JR., David B. Stone
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Patent number: 9057760Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.Type: GrantFiled: January 20, 2011Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Luke D. Lacroix, Mark C. H. Lamorey, Steven F. Oakland, Janak G. Patel, Kerry P. Pfarr, Peter Slota, Jr., David B. Stone
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Publication number: 20150070048Abstract: Structures, methods, and systems for designing and verifying integrated circuits including redundant logic blocks are provided. An integrated circuit includes selection logic and selectable logic blocks that are individually controllable by the selection logic. The selectable logic blocks include respective instances of a redundant logic block, and respective instances of an interface logic block that selectively disable the redundant logic blocks in the integrated circuit.Type: ApplicationFiled: September 6, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: Kevin W. GORMAN, Steven F. OAKLAND, Michael R. OUELLETTE, Steven J. URISH
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Patent number: 8423844Abstract: A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.Type: GrantFiled: January 11, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Pamela S. Gillis, David E. Lackey, Steven F. Oakland, Jeffery H. Oppold
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Patent number: 8423847Abstract: Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.Type: GrantFiled: May 11, 2012Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Gary D. Grise, David E. Lackey, Steven F. Oakland, Donald L. Wheater
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Publication number: 20120221910Abstract: Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.Type: ApplicationFiled: May 11, 2012Publication date: August 30, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary D. GRISE, David E. LACKEY, Steven F. OAKLAND, Donald L. Wheater
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Publication number: 20120187953Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.Type: ApplicationFiled: January 20, 2011Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luke D. LACROIX, Mark C.H. Lamorey, Steven F. Oakland, Janak G. Patel, Kerry P. Pfarr, Peter Slota, JR., David B. Stone
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Patent number: 8230283Abstract: A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i.e., shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse.Type: GrantFiled: December 18, 2009Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Pamela S. Gillis, Vikram Iyengar, Steven F. Oakland
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Publication number: 20120179944Abstract: A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.Type: ApplicationFiled: January 11, 2011Publication date: July 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pamela S. Gillis, David E. Lackey, Steven F. Oakland, Jeffery H. Oppold
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Patent number: 8205124Abstract: Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.Type: GrantFiled: November 11, 2008Date of Patent: June 19, 2012Assignee: International Business Machines CorporationInventors: Gary D. Grise, David E. Lackey, Steven F. Oakland, Donald L. Wheater
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Patent number: 8181135Abstract: A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.Type: GrantFiled: August 27, 2009Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Vikram Iyengar, Pamela S. Gillis, David E. Lackey, Steven F. Oakland
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Publication number: 20110154141Abstract: A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i.e., shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pamela S. Gillis, Vikram Iyengar, Steven F. Oakland
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Publication number: 20110055650Abstract: A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.Type: ApplicationFiled: August 27, 2009Publication date: March 3, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vikram Iyengar, Pamela S. Gillis, David E. Lackey, Steven F. Oakland
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Patent number: 7840864Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.Type: GrantFiled: December 10, 2009Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Gary D. Grise, Steven F. Oakland, Anthony D. Polson, Philip S. Stevens
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Patent number: 7840863Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.Type: GrantFiled: December 10, 2009Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Gary D. Grise, Steven F. Oakland, Anthony D. Polson, Philip S. Stevens
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Patent number: 7823035Abstract: A system and methods of balancing scan chains and, more particularly, a system and methods of load balancing scan chains into hierarchically designed integrated circuits. The method includes estimating or calculating a maximum scan chain length L and creating a maximum number of scan chains of length L in each hierarchical block. The method further includes distributing remaining scan bits in each hierarchical block into additional scan chains, and creating chip-level scan chains by using the scan chains of maximum length L and by forming additional chip-level scan chains of maximum length L by distributing the additional scan chains of maximum length LR, plus any remaining top-level scan bits, among the additional chip-level scan chains of maximum length L.Type: GrantFiled: May 15, 2007Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: David D. Litten, Steven F. Oakland
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Patent number: 7698611Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.Type: GrantFiled: July 2, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Gary Grise, Steven F. Oakland, Anthony S. Polson, Philip S. Stevens
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Publication number: 20100088562Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.Type: ApplicationFiled: December 10, 2009Publication date: April 8, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary D. Grise, Steven F. Oakland, Anthony D. Polson, Philip S. Stevens