Patents by Inventor Steven F. Schicht
Steven F. Schicht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11038492Abstract: In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.Type: GrantFiled: August 19, 2019Date of Patent: June 15, 2021Assignee: Apple Inc.Inventors: Steven F. Schicht, William R. Weier
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Publication number: 20190372559Abstract: In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.Type: ApplicationFiled: August 19, 2019Publication date: December 5, 2019Inventors: Steven F. Schicht, William R. Weier
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Patent number: 10389335Abstract: In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.Type: GrantFiled: May 4, 2018Date of Patent: August 20, 2019Assignee: Apple Inc.Inventors: Steven F. Schicht, William R. Weier
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Patent number: 6487681Abstract: A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described.Type: GrantFiled: November 9, 1999Date of Patent: November 26, 2002Assignee: Micron Technology, Inc.Inventors: Mark E. Tuttle, Rickie C. Lake, Steven F. Schicht, John R. Tuttle
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Patent number: 6366523Abstract: A method and apparatus are disclosed for selecting either an external column address or an internal column address in a synchronous memory device. The external or internal address is selected by decoding command signals applied to the memory device. If the command signals correspond to a read or a write memory access, an external column address is selected. If the command signals correspond to a burst read or write memory access, an internal column address is selected. Significantly, the command signals are decoded prior to the transition of a clock signal that initiates a memory access so that a column address decoder is already connected to the proper column address source prior to the start of a memory access.Type: GrantFiled: September 5, 2000Date of Patent: April 2, 2002Assignee: Micron Technology, Inc.Inventors: Jeffrey P. Wright, Steven F. Schicht
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Patent number: 6163863Abstract: A test circuit in a memory device includes test data read paths and test data write paths for performing data compression to more quickly test the memory cells in the memory device. The memory device includes first and second banks of memory cells having a redundancy plane defined between the two banks and including at least one data terminal. The test circuit includes a test mode terminal adapted to receive a test mode signal, and a test data write path coupled to a plurality of memory cells in the first and second banks. The test circuit further includes a first test data read path coupled to a plurality of memory cells in the first bank, and a second test data read path coupled to a plurality of memory cells in the second bank. A test data write circuit is coupled to the data terminal and to the test data write path and transfers test data placed on the data terminal over the test data write path to a plurality of memory cells in the first and second banks.Type: GrantFiled: May 22, 1998Date of Patent: December 19, 2000Assignee: Micron Technology, Inc.Inventor: Steven F. Schicht
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Patent number: 6115314Abstract: A method and apparatus are disclosed for selecting either an external column address or an internal column address in a synchronous memory device. The external or internal address is selected by decoding command signals applied to the memory device. If the command signals correspond to a read or a write memory access, an external column address is selected. If the command signals correspond to a burst read or write memory access, an internal column address is selected. Significantly, the command signals are decoded prior to the transition of a clock signal that initiates a memory access so that a column address decoder is already connected to the proper column address source prior to the start of a memory access.Type: GrantFiled: June 15, 1999Date of Patent: September 5, 2000Assignee: Micron Technology, Inc.Inventors: Jeffrey P. Wright, Steven F. Schicht
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Patent number: 6026496Abstract: A circuit for generating a pulse with minimal delay after receiving a trigger signal includes a passgate, a gating circuit, and a reset circuit. The passgate is enabled by control signals received at the gating circuit having a trigger signal as one of the control signals. The trigger signal is also presented as an input to the passgate. When enabled, the passgate propagates the trigger signal to an output. A predetermined time after the trigger signal appears at the passgate input, a passgate control signal is turned off, thereby preventing the trigger signal from further passing through the passgate. The reset circuit is then turned on, which pulls the signal at the output of the passgate to a reference voltage, ending the pulse. Once the pulse is generated, it can be rectified and further combined with other signals to produce signals used in other parts of the circuit.Type: GrantFiled: December 31, 1997Date of Patent: February 15, 2000Assignee: Micron Technology, Inc.Inventors: Jeffrey P. Wright, Steven F. Schicht
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Patent number: 5983363Abstract: A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described.Type: GrantFiled: September 15, 1994Date of Patent: November 9, 1999Assignee: Micron Communications, Inc.Inventors: Mark E. Tuttle, Rickie C. Lake, Steven F. Schicht, John R. Tuttle
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Patent number: 5936479Abstract: An oscillator circuit is described which produces a periodic oscillator output signal. The frequency of the oscillator output signal is essentially independent of the supply voltage provided to the oscillator circuit. The oscillator circuit includes a capacitor which is periodically charged and discharged. A high trip point inverter and a low trip point inverter detect the voltage level of the capacitor and set and reset, respectively, a flip-flop. The flip-flop produces an output signal which controls the charge and discharge of the capacitor through charging and discharging circuit paths, respectively. The impedance presented by the charging and discharging circuit paths varies as a function of the supply voltage, such that the high and low trip point inverters are switched at a frequency which is essentially independent of the supply voltage magnitude. The oscillator output signal is derived from the flip-flop output signal.Type: GrantFiled: December 24, 1997Date of Patent: August 10, 1999Assignee: Micron Technology, Inc.Inventors: Donald M. Morgan, Steven F. Schicht
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Patent number: 5923604Abstract: A method and apparatus are disclosed for selecting either an external column address or an internal column address in a synchronous memory device. The external or internal address is selected by decoding command signals applied to the memory device. If the command signals correspond to a read or a write memory access, an external column address is selected. If the command signals correspond to a burst read or write memory access, an internal column address is selected. Significantly, the command signals are decoded prior to the transition of a clock signal that initiates a memory access so that a column address decoder is already connected to the proper column address source prior to the start of a memory access.Type: GrantFiled: December 23, 1997Date of Patent: July 13, 1999Assignee: Micron Technology, Inc.Inventors: Jeffrey P. Wright, Steven F. Schicht
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Patent number: RE38903Abstract: A circuit for generating a pulse with minimal delay after receiving a trigger signal includes a passgate, a gating circuit, and a reset circuit. The passgate is enabled by control signals received at the gating circuit having a trigger signal as one of the control signals. The trigger signal is also presented as an input to the passgate. When enabled, the passgate propagates the trigger signal to an output. A predetermined time after the trigger signal appears at the passgate input, a passgate control signal is turned off, thereby preventing the trigger signal from further passing through the passgate. The reset circuit is then turned on, which pulls the signal at the output of the passgate to a reference voltage, ending the pulse. Once the pulse is generated, it can be rectified and further combined with other signals to produce signals used in other parts of the circuit.Type: GrantFiled: February 14, 2002Date of Patent: November 29, 2005Assignee: Micron Technology, Inc.Inventors: Jeffrey P. Wright, Steven F. Schicht
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Patent number: RE42872Abstract: A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described. Flexible radio frequency identification (RFID) devices are coupled to a roll of flexible material. Each RFID device coupled to the roll is advanced into a wireless communication region. An antenna in the region separately communicates with each of the RFID devices in a manner that isolates the communication from other REID devices counted to the roll outside the region.Type: GrantFiled: November 24, 2004Date of Patent: October 25, 2011Assignee: Round Rock Research, LLCInventors: Mark E. Tuttle, Rickie C. Lake, Steven F. Schicht, John R. Tuttle
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Patent number: RE43918Abstract: A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described. An RFID tag and interrogator may each include a transmitter and a receiver. The tag and interrogator may communicate with each other at different frequency bands and may communicate in accordance with a wireless communication protocol.Type: GrantFiled: September 28, 2007Date of Patent: January 8, 2013Assignee: Round Rock Research, LLCInventors: Mark E. Tuttle, Rickie C. Lake, Steven F. Schicht, John R. Tuttle
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Patent number: RE43935Abstract: A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described. An RFID tag and interrogator may each include a transmitter and a receiver. The tag and interrogator may communicate with each other at different frequency bands and may communicate in accordance with a wireless communication protocol.Type: GrantFiled: September 28, 2007Date of Patent: January 15, 2013Assignee: Round Rock Research, LLCInventors: Mark E. Tuttle, Rickie C. Lake, Steven F. Schicht, John R. Tuttle
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Patent number: RE43940Abstract: A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described. An RFID tag and interrogator may each include a transmitter and a receiver. The tag and interrogator may communicate with each other at different frequency bands and may communicate in accordance with a wireless communication protocol.Type: GrantFiled: September 28, 2007Date of Patent: January 22, 2013Assignee: Round Rock Research, LLCInventors: Mark E. Tuttle, Rickie C. Lake, Steven F. Schicht, John R. Tuttle