Patents by Inventor Steven F. Weiss

Steven F. Weiss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pipeline structure for a shared memory protocol
    Patent number: 8028130
    Abstract: A method and apparatus for implementation of a pipeline structure for data transfer. A request is received from a first domain to access a second domain during a first clock cycle. A pipeline structure is used to perform at least a portion of the request during a subsequent clock cycle.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: September 27, 2011
    Assignee: Oracle America, Inc.
    Inventors: Steven F. Weiss, Andrew E. Phelps, Patricia Shanahan
  • System design verification using selected states of a processor-based system to reveal deficiencies
    Patent number: 6920584
    Abstract: The present invention provides a method and apparatus for design verification. The method comprises operating a device in the system in a first state, modifying at least one operational characteristic of the device to operate in a second state, and determining if an error condition occurs in the system in response to modifying the operational characteristic of the device. The apparatus comprises an interface and a verification module adapted to receive a control signal from the interface and to adjust an operating characteristic of the apparatus to exercise a system in a manner that is capable of revealing one or more error conditions in the system in response to receiving the control signal.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: July 19, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Andrew E. Phelps, Steven F. Weiss
  • Cage for dynamic attach testing of I/O boards
    Patent number: 6571360
    Abstract: A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: May 27, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Daniel P. Drogichen, Eric Eugene Graf, Don Kane, Douglas B. Meyer, Andrew E. Phelps, Patricia Shanahan, Steven F. Weiss
  • Design verification
    Publication number: 20030088808
    Abstract: The present invention provides a method and apparatus for design verification. The method comprises operating a device in the system in a first state, modifying at least one operational characteristic of the device to operate in a second state, and determining if an error condition occurs in the system in response to modifying the operational characteristic of the device. The apparatus comprises an interface and a verification module adapted to receive a control signal from the interface and to adjust an operating characteristic of the apparatus to exercise a system in a manner that is capable of revealing one or more error conditions in the system in response to receiving the control signal.
    Type: Application
    Filed: November 2, 2001
    Publication date: May 8, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: Andrew E. Phelps, Steven F. Weiss