Patents by Inventor Steven G. Esposito

Steven G. Esposito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10162920
    Abstract: The present disclosure relates to systems and methods for performing out of order name resolution in an electronic design language. Embodiments may include receiving, one or more design units associated with an electronic design and registering the one or more design units in a registry database. Embodiments may further include performing local name resolution for each element reference within at least one of the one or more design units. In response to registering, embodiments include identifying at least one element reference upon which local name resolution was not performed and obtaining an appropriate element reference from the registry database. Embodiments may further include reviewing at least one secondary design unit for one or more local declarations and performing local name resolution for one or more remaining element references using a design hierarchy.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: December 25, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jonathan Lee DeKock, Steven G. Esposito, Manu Chopra, Meir Ovadia
  • Patent number: 8689187
    Abstract: A test object can be selectively included in a test run based on predicting the behavior of the test object. In one embodiment, the present invention includes predicting how likely the test object is to produce a failure in a test run and deciding whether to include the test object in the test run based on the predicted likelihood. This likelihood of producing a failure may be based on any number of circumstances. For example, these circumstances may include the history of prior failures and/or the length of time since the test object was last included in a test run.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: April 1, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven G. Esposito, Kiran Chhabra, Saran Prasad, D. Scott Baeder
  • Publication number: 20080282124
    Abstract: A test object can be selectively included in a test run based on predicting the behavior of the test object. In one embodiment, the present invention includes predicting how likely the test object is to produce a failure in a test run and deciding whether to include the test object in the test run based on the predicted likelihood. This likelihood of producing a failure may be based on any number of circumstances. For example, these circumstances may include the history of prior failures and/or the length of time since the test object was last included in a test run.
    Type: Application
    Filed: May 7, 2007
    Publication date: November 13, 2008
    Inventors: Steven G. Esposito, Kiran Chhabra, Saran Prasad, D. Scott Baeder