Patents by Inventor Steven G. H. Anderson

Steven G. H. Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160109506
    Abstract: A semiconductor device includes a substrate, first electronic circuitry formed on the substrate, a first diode buried in the substrate under the first electronic circuitry, and a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 21, 2016
    Inventors: MARK D. HALL, STEVEN G.H. ANDERSON, MEHUL D. SHROFF
  • Patent number: 6964902
    Abstract: Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: November 15, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert F. Steimle, Jane A. Yater, Gowrishankar L. Chindalore, Craig T. Swift, Steven G. H. Anderson, Ramachandran Muralidhar
  • Patent number: 6849487
    Abstract: A method of forming a conductive structure having a length that is less than the length define by photolithographic patterning. A silicon layer (12) is formed in a MeOx dielectric layer (11) is photolithographically patterned to a predetermined first length. A metal layer (31) is formed conformally to at least the sidewalls of the silicon layer and then is reacted with the silicon to form a metal silicide (41). In particular, metal silicide abutments (411,412) are formed contiguous to sidewalls (421,422) of a reduced conductor (42). The remaining metal layer and the metal silicide are etched away, resulting in a conductor having predetermined second length that is less than the predetermined first length.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: February 1, 2005
    Assignee: Motorola, Inc.
    Inventors: William J. Taylor, Jr., Olubunmi O. Adetutu, Steven G. H. Anderson
  • Publication number: 20040253799
    Abstract: A method of forming a conductive structure having a length that is less than the length defined by photolithographic patterning. A silicon layer (12) is formed in a MeOx dielectric layer (11). The silicon layer is photolithographically patterned to a predetermined first length. A metal layer (31) is formed conformally to at least the sidewalls of the silicon layer and then is reacted with the silicon to form a metal silicide (41). In particular, metal silicide abutments (411,412) are formed contiguous to sidewalls (421,422) of a reduced conductor (42). The remaining metal layer and the metal silicide are etched away, resulting in a conductor having predetermined second length that is less than the predetermined first length.
    Type: Application
    Filed: May 27, 2003
    Publication date: December 16, 2004
    Inventors: William J. Taylor, Olubunmi O. Adetutu, Steven G. H. Anderson