Abstract: There is disclosed a horizontal transversal multiplexer which operates and controls an associative array. The associative array consists of a plurality of processor cells which are arranged in an N X M matrix. The transversal horizontal multiplexer constitutes apparatus which allows great flexibility concerning data flow through the processor cells. The multiplexer includes means for transferring data in a right or a left direction from cell to cell and further includes means for bypassing any cell to increase the flexibility of the associative array. The multiplexer has four signal nodes each providing a single bit path and has control inputs with a left signal node connected to the right signal input of a left neighboring processor cell and with the right signal node connected to the left signal input of a right neighboring processor cell in said array. One of the nodes constitute a data input node and the other node is a data output node.

Abstract: An improved circuit for performing high speed arithmetic computations is described, and includes a mechanism for dynamically deleting faulty data bits in a configuration for minimizing propagation delay paths. The invention is particularly applicable to an associative processor wherein the data word length and rate of flow of data may vary from one instruction to the next. In accordance with the invention, data propagation delay time is minimized as is the number of required circuit interconnections, thereby making the invention easily manufacturable on an LSI chip. The advantages of the circuit design are multiplied in an associative processor, since such processors are highly reconfigurable and must be able to exclude unwanted bits from an arithmetic operation, to change data word sizes and to delete failed bits.