Abstract: In performing a series of device evaluation cycles relative to pins of a physical electronic model, a signature associated with an immediately preceding device evaluation cycle is compared to the corresponding signature that exists just prior to the last pattern for the current device evaluation cycle. If the signatures compare, the new pattern of the current evaluation cycle is completed. If the signatures do not compare, an error has occurred and the operator is notified so that this series of device evaluation cycles will not be considered valid. Computer simulation information is employed to determine the optimal times to clock signatures with each signal pin having its own programmable clocking circuit. These optimally generated signatures are used to verify the consistent operation of the physical model.