Patents by Inventor Steven G. Seidel

Steven G. Seidel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor die manufacture method to limit a voltage drop on a power plane thereof by noninvasively measuring voltages on a power plane
    Patent number: 6519744
    Abstract: A method is provided for manufacturing a die. A supply voltage is provided to a power plane of a selected integrated circuit, formed in and on a semiconductor substrate, having a selected design, so that a respective test current flows through a plurality of test elements, of the selected integrated circuit, each being connected to a respective test point on the power plane, the test points being spaced from one another. A magnitude of each respective test current is detected. A respective test voltage is calculated at each respective test point utilizing the respective magnitude of the respective test current flowing through the respective test element connected to a respective test point. The respective test voltages are utilized to determine at which ones of the test points the respective test voltages are more than a predetermined maximum below a supply voltage.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: February 11, 2003
    Assignee: Intel Corporation
    Inventors: Steven G. Seidel, Travis M. Eiles, Gary L. Woods, Stefan Rusu, Dean J. Grannes
  • Semiconductor die manufacture method to limit a voltage drop on a power plane thereof by noninvasively measuring voltages on a power plane
    Publication number: 20020073386
    Abstract: A method is provided for manufacturing a die. A supply voltage is provided to a power plane of a selected integrated circuit, formed in and on a semiconductor substrate, having a selected design, so that a respective test current flows through a plurality of test elements, of the selected integrated circuit, each being connected to a respective test point on the power plane, the test points being spaced from one another. A magnitude of each respective test current is detected. A respective test voltage is calculated at each respective test point utilizing the respective magnitude of the respective test current flowing through the respective test element connected to a respective test point. The respective test voltages are utilized to determine at which ones of the test points the respective test voltages are more than a predetermined maximum below a supply voltage.
    Type: Application
    Filed: December 12, 2000
    Publication date: June 13, 2002
    Inventors: Steven G. Seidel, Travis M. Eiles, Gary L. Woods, Stefan Rusu, Dean J. Grannes