Abstract: Described are systems and methods for internal log management in memory sub-systems. An example memory sub-system comprises a controller managing one or more memory devices.

Abstract: Memory with efficient storage of event log data is disclosed herein. In one embodiment, a memory device includes a non-volatile memory subsystem storing a persistent event log file, and a volatile memory subsystem including a working buffer. The memory device is configured to write newly generated event log data of the memory device to the working buffer. The memory device is further configured to write the newly generated first event log data to a first subregion of the persistent event log file. The first subregion can be one of a plurality of subregions of the persistent event log file, and can correspond to an end of event log data stored to the persistent event log file. The volatile memory subsystem can be positioned inside or outside a controller operably connected to the non-volatile memory subsystem.

Abstract: Memory with efficient storage of event log data is disclosed herein. In one embodiment, a memory device includes a non-volatile memory subsystem storing a persistent event log file, and a volatile memory subsystem including a working buffer. The memory device is configured to write newly generated event log data of the memory device to the working buffer. The memory device is further configured to write the newly generated first event log data to a first subregion of the persistent event log file. The first subregion can be one of a plurality of subregions of the persistent event log file, and can correspond to an end of event log data stored to the persistent event log file. The volatile memory subsystem can be positioned inside or outside a controller operably connected to the non-volatile memory subsystem.

Abstract: Memory with efficient storage of event log data is disclosed herein. In one embodiment, a memory device includes a non-volatile memory subsystem storing a persistent event log file, and a volatile memory subsystem including a working buffer. The memory device is configured to write newly generated event log data of the memory device to the working buffer. The memory device is further configured to write the newly generated first event log data to a first subregion of the persistent event log file. The first subregion can be one of a plurality of subregions of the persistent event log file, and can correspond to an end of event log data stored to the persistent event log file. The volatile memory subsystem can be positioned inside or outside a controller operably connected to the non-volatile memory subsystem.

Abstract: A processing device in a memory system determines to send system state information associated with the memory device to a host system and identifies a subset of a plurality of event entries from a staging buffer based on one or more filtering factors, the plurality of event entries corresponding to events associated with the memory device. The processing device further sends the subset of the plurality of event entries as the system state information to the host system over a communication pipe having limited bandwidth.

Abstract: A processing device in a memory system determines to send system state information associated with the memory device to a host system and identifies a subset of a plurality of event entries from a staging buffer based on one or more filtering factors, the plurality of event entries corresponding to events associated with the memory device. The processing device further sends the subset of the plurality of event entries as the system state information to the host system over a communication pipe having limited bandwidth.

Abstract: A processing device in a memory system determines to send system state information associated with the memory device to a host system and identifies a subset of a plurality of event entries from a staging buffer based on one or more filtering factors, the plurality of event entries corresponding to events associated with the memory device. The processing device further sends the subset of the plurality of event entries as the system state information to the host system over a communication pipe having limited bandwidth.

Abstract: A processing device in a memory system receives a privilege key from a host system, the privilege key having an associated level of access to debug information associated with the memory device and determines the level of access associated with the privilege key. The processing device receives, from the host system, a request for debug information directed to a debug slave address associated with a system management bus port of a memory sub-system, identifies the debug information corresponding to the level of access associated with the privilege key, and sends the debug information to the host system over a system management bus coupled to the system management bus port of the memory sub-system.

Abstract: A processing device in a memory system receives, from a host system, a request for a debug slave address associated with a system management bus port of a memory sub-system and sends a response comprising the debug slave address to the host system. The processing device receives, from the host system, a request to enable the system management bus port to receive a request for debug information directed to the debug slave address, receives, from the host system, the request for debug information directed to the debug slave address, and sends the debug information to the host system over a system management bus coupled to the system management bus port of the memory sub-system.

Abstract: A processing device in a memory system receives, from a host system, a request for a debug slave address associated with a system management bus port of a memory sub-system and sends a response comprising the debug slave address to the host system. The processing device receives, from the host system, a request to enable the system management bus port to receive a request for debug information directed to the debug slave address, receives, from the host system, the request for debug information directed to the debug slave address, and sends the debug information to the host system over a system management bus coupled to the system management bus port of the memory sub-system.

Abstract: A processing device in a memory system receives a privilege key from a host system, the privilege key having an associated level of access to debug information associated with the memory device and determines the level of access associated with the privilege key. The processing device receives, from the host system, a request for debug information directed to a debug slave address associated with a system management bus port of a memory sub-system, identifies the debug information corresponding to the level of access associated with the privilege key, and sends the debug information to the host system over a system management bus coupled to the system management bus port of the memory sub-system.

Abstract: A sensor system can include a sensor coil and a sensor coupled to the sensor coil. The sensor coil can include coil portions that generate signals based on magnetic coupling induced in the coil portions by a receiving coil device (e.g., a NFC tag) and magnetic distortion induced in the coil portions by magnetic coupling of a power transmitting unit (PTU). The sensor can reduce the magnetic distortion induced in the first and the second coil portions by the PTU, detect the receiving coil device based the first and the second signals, and control the PTU based on the detected receiving coil device.

Abstract: A processing device in a memory system determines to send system state information associated with the memory device to a host system and identifies a subset of a plurality of event entries from a staging buffer based on one or more filtering factors, the plurality of event entries corresponding to events associated with the memory device. The processing device further sends the subset of the plurality of event entries as the system state information to the host system over a communication pipe having limited bandwidth.

Abstract: A Solid-State Disk (SSD) Manufacturing Self Test (MST) capability enables an SSD manufacturer to generate and load tests onto SSDs, run the tests, and gather results. The SSDs self execute the loaded tests when powered up. The self executing is while coupled to a host that loaded the tests or while coupled to a rack unable to load the tests but enabled to provide power to the SSDs. The rack is optionally cost-reduced to enable cost-efficient parallel testing of relatively larger numbers of SSDs for production. The host writes the tests to an ‘input’ SMART log of each SSD, and each SSD writes results to a respective included ‘output’ SMART log. The commands include write drive, erase drive, SATA PHY burn-in, delay, and stress mode. The SSD MST capability is optionally used in conjunction with an SSD virtual manufacturing model.

Abstract: Exemplary methods, apparatuses, and systems include firmware for the non-volatile storage device, during boot up, dynamically allocating volatile memory to a plurality of storage management components. The allocation includes detecting an indicator of a total amount of volatile memory to be allocated to the storage management components. The firmware maps the indicator to a first amount of volatile memory to allocate to a first set of one or more components and allocates the first amount of the volatile memory to the first set of components. The firmware allocates remaining volatile memory to a flash translation layer.

Abstract: Methods and systems configured to increment one or more counters, including read command total, write command total, total blocks written and read, and low read or write queue depth, when a read or write command is received. When a request for a total device busy time is received, a total device busy time is determined and provided using one or more of the counters and one or more corresponding timing factors.

Abstract: A processing device stores a first log entry in a first log structure that stores log entries regarding occurrences of events for a first core in a computer system composed of a plurality of cores. In response to detecting the occurrence of a log flush trigger event, the processing device copies a plurality of log entries, including the first log entry, from the first log structure as a second log entry in a second log structure that stores log entries for multiple of the plurality of cores. The processing device dynamically determines the size of the second log entry based on the varied sizes of the plurality of log entries. The processing device generates a log entry header for the second log entry, including at least a core identifier identifying the first core associated with the first log structure and prepends the log entry header to the second log entry.

Abstract: Methods and systems configured to increment one or more counters, including read command total, write command total, total blocks written and read, and low read or write queue depth, when a read or write command is received. When a request for a total device busy time is received, a total device busy time is determined and provided using one or more of the counters and one or more corresponding timing factors.

Abstract: A processing device stores a first log entry in a first log structure that stores log entries regarding occurrences of events for a first core in a computer system composed of a plurality of cores. In response to detecting the occurrence of a log flush trigger event, the processing device copies a plurality of log entries, including the first log entry, from the first log structure as a second log entry in a second log structure that stores log entries for multiple of the plurality of cores. The processing device dynamically determines the size of the second log entry based on the varied sizes of the plurality of log entries. The processing device generates a log entry header for the second log entry, including at least a core identifier identifying the first core associated with the first log structure and prepends the log entry header to the second log entry.

Abstract: Exemplary methods, apparatuses, and systems include firmware for the non-volatile storage device, during boot up, dynamically allocating volatile memory to a plurality of storage management components. The allocation includes detecting an indicator of a total amount of volatile memory to be allocated to the storage management components. The firmware maps the indicator to a first amount of volatile memory to allocate to a first set of one or more components and allocates the first amount of the volatile memory to the first set of components. The firmware allocates remaining volatile memory to a flash translation layer.