Abstract: Asynchronous/plesiochronous digital hierarchy (PDH) signals, such as DS1 and E1, are transported using virtual concatenation. The packetized data signals are frame encapsulated and subsequently inverse multiplexed into a plurality of PDH frames. An overhead packet is inserted in the transmitted frames to enable the receiver to determine the status of the frames and extract the differential delay experienced by various frames as they are routed through virtually concatenated channels. The extracted delays enables the receiver to realign the various frames of the PDH signal to reconstitute the originally transmitted signals that travel through different paths of the transport network linking the source and sink of the virtually concatenated channel.

Abstract: The present invention provides a circuit for detecting and correcting errors in a bit stream. The circuit consists of a plurality of circuit elements, a least one operation circuit means, and at least two logic gates. The logic gates receive inputs from the plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. The operation circuit elements perform bitwise operations on the contents of at least two of the circuit elements. The bitwise operations are dictated by a cyclical redundancy check (CRC) polynomial and are used to perform the CRC error detection division operation. At the end of the division process for the data to be checked, each circuit element corresponds to a bit in a bit error pattern syndrome and the logic gates determine if the contents of the circuit elements match specific bit error patterns.

Abstract: The present invention provides a circuit for detecting and correcting errors in a bit stream. The circuit consists of a plurality of circuit elements, a least one operation circuit means, and at least two logic gates. The logic gates receive inputs from the plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. The operation circuit elements perform bitwise operations on the contents of at least two of the circuit elements. The bitwise operations are dictated by a cyclical redundancy check (CRC) polynomial and are used to perform the CRC error detection division operation. At the end of the division process for the data to be checked, each circuit element corresponds to a bit in a bit error pattern syndrome and the logic gates determine if the contents of the circuit elements match specific bit error patterns.