Abstract: A method, system and program product are disclosed for statistical modeling an integrated circuit that provides information about partial correlations between model parameters. The invention determines a variance-covariance matrix for data to be modeled; conducts principal component analysis on the variance-covariance matrix; and creates a statistical model with an independent distribution for each principal component, allowing calculation of each individual model parameter as a weighted sum by a circuit simulator. The statistical model provides information about how well individual transistors will track one another based on layout similarity. This allows the designer to quantify and take advantage of design practices that make all transistors similar, for example, by orienting all gates in the same direction. A method, system and program product for simulating a circuit using the statistical model are also included.

Abstract: The invention encompasses memory systems and/or memory modules which allow selectable clock termination between the clock/clock buffer and components of the memory modules. The invention provides a fully forward and backward compatible memory solution. The invention provides the memory modules themselves, the FET switches designed for use on the modules, and the systems that include enable/disable pins to use these modules. This invention will permit memory modules to be developed that can operate in existing (emerging) memory subsystems, as well as meet the low power/low pin count needs of future memory subsystems with no required changes to the existing/emerging systems. For 184 Pin Registered DIMMs, the power savings will equate to greater than 200 mw/DIMM, and systems will be permitted to connect DIMM clocks in serial, similar to address/control lines, thereby increasing the address/control window as well as the system read loop-back timings.

Abstract: The invention encompasses memory systems and/or memory modules which allow selectable clock termination between the clock/clock buffer and components of the memory modules. The invention provides a fully forward and backward compatible memory solution. The invention provides the memory modules themselves, the FET switches designed for use on the modules, and the systems that include enable/disable pins to use these modules. This invention will permit memory modules to be developed that can operate in existing (emerging) memory subsystems, as well as meet the low power/low pin count needs of future memory subsystems with no required changes to the existing/emerging systems. For 184 Pin Registered DIMMs, the power savings will equate to greater than 200 mw/DIMM, and systems will be permitted to connect DIMM clocks in serial, similar to address/control lines, thereby increasing the address/control window as well as the system read loop-back timings.