Abstract: A method, system and program product are disclosed for statistical modeling an integrated circuit that provides information about partial correlations between model parameters. The invention determines a variance-covariance matrix for data to be modeled; conducts principal component analysis on the variance-covariance matrix; and creates a statistical model with an independent distribution for each principal component, allowing calculation of each individual model parameter as a weighted sum by a circuit simulator. The statistical model provides information about how well individual transistors will track one another based on layout similarity. This allows the designer to quantify and take advantage of design practices that make all transistors similar, for example, by orienting all gates in the same direction. A method, system and program product for simulating a circuit using the statistical model are also included.

Abstract: A method, system and program product are disclosed for statistical modeling an integrated circuit that provides information about partial correlations between model parameters. The invention determines a variance-covariance matrix for data to be modeled; conducts principal component analysis on the variance-covariance matrix; and creates a statistical model with an independent distribution for each principal component, allowing calculation of each individual model parameter as a weighted sum by a circuit simulator. The statistical model provides information about how well individual transistors will track one another based on layout similarity. This allows the designer to quantify and take advantage of design practices that make all transistors similar, for example, by orienting all gates in the same direction. A method, system and program product for simulating a circuit using the statistical model are also included.

Abstract: The invention encompasses memory systems and/or memory modules which allow selectable clock termination between the clock/clock buffer and components of the memory modules. The invention provides a fully forward and backward compatible memory solution. The invention provides the memory modules themselves, the FET switches designed for use on the modules, and the systems that include enable/disable pins to use these modules. This invention will permit memory modules to be developed that can operate in existing (emerging) memory subsystems, as well as meet the low power/low pin count needs of future memory subsystems with no required changes to the existing/emerging systems. For 184 Pin Registered DIMMs, the power savings will equate to greater than 200 mw/DIMM, and systems will be permitted to connect DIMM clocks in serial, similar to address/control lines, thereby increasing the address/control window as well as the system read loop-back timings.

Abstract: A Synchronous DRAM memory test assembly that converts a normal PC or Workstation with a synchronous bus into a memory tester. The test assembly may be split into two segments: a diagnostic card and an adapter card to limit mechanical load on the system socket as well as permit varying form factors. This test assembly architecture supports memory bus speeds of 66 MHz and above, and provides easy access for a logic analyzer. The test assembly supports Registered and Unbuffered Synchronous DRAM products. The test assembly permits good and questionable synchronous modules to be compared using an external logic analyzer. It permits resolution of in-system fails that occur uniquely in system environments and may be otherwise difficult or impossible to replicate.

Abstract: The invention encompasses memory systems and/or memory modules which allow selectable clock termination between the clock/clock buffer and components of the memory modules. The invention provides a fully forward and backward compatible memory solution. The invention provides the memory modules themselves, the FET switches designed for use on the modules, and the systems that include enable/disable pins to use these modules. This invention will permit memory modules to be developed that can operate in existing (emerging) memory subsystems, as well as meet the low power/low pin count needs of future memory subsystems with no required changes to the existing/emerging systems. For 184 Pin Registered DIMMs, the power savings will equate to greater than 200 mw/DIMM, and systems will be permitted to connect DIMM clocks in serial, similar to address/control lines, thereby increasing the address/control window as well as the system read loop-back timings.

Abstract: The disclosed invention relates generally to electronic data storage systems that access data storage memory modules via a data bus comprised of multiple data query lines and, more particularly, to an electronic data storage system provided with a data bus that can be selectively provided with terminations thereby permitting the data storage memory to use either modules that require that the data query lines be open-ended, i.e., without terminations or modules that require that the data bus be terminated and to a method for operating such a system. The present invention is particularly directed to a single memory system that can accommodate either 3.3V DIMMs or DDR DIMMs. This is especially accomplished by providing the processor circuit, used in memory storage systems, with both (3.

Abstract: This discloses a memory module adapter card that allows newer dual in-line memory modules (DIMMs) to be used by computer system boards that were built to use older single inline memory modules (SIMMs) thereby permitting computer owners to update and upgrade older machines without modifying or changing their system boards. This memory module adapter card is designed to connect a memory DIMM inserted into a DIMM socket, carried thereon, to a pair of smaller SIMM sockets on a computer system board such that the DIMM appears to the computer as a pair of the smaller SIMMs that the board was originally designed for. This decreases the need for manufacturing and maintaining an inventory of the older SIMMs and provides owners of older computers the means to extend the useful life of their existing computer system even if the SIMMs designed for the computer no longer exist or are prohibitively expensive or very difficult to locate.

Abstract: A PCMCIA card comprises a plurality of I/O functions. Each has an interrupt signal, but the card has only one interrupt request (IREQ) line. The card is provided with an interrupt status register (ISR) to receive the interrupt signals from each of the I/O functions. This ISR allows software to determine the function that signaled the interrupt. The card is also provided with interrupt control logic (ICL) that is responsive to the interrupt status of ISR. The ICL sends an IREQ signal to a host system.

Abstract: Disclosed is a process for depositing a conformal polymer coating on selected areas of a silicon substrate. The substrate is first exposed through a mask to a gaseous plasma so as to form a film of desired pattern, the plasma comprising a compound having strong electron donating characteristics. Then, the patterned film and the remaining substrate not covered by the film are exposed to the vapor of a monomer, which condenses and polymerizes on the exposed substrate surfaces, but not on the film. The film serves to inhibit substantial deposition of the coating, so as to provide a selective deposition, where the coating is formed only on those areas of the substrate where desired.