Patents by Inventor Steven Grzeskowiak

Steven Grzeskowiak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250138429
    Abstract: A method of endpoint detection includes performing a surface treatment on a wafer without plasma in a process chamber which includes an outlet configured to output an exhaust gas of the surface treatment. An exhaust plasma is generated from the exhaust gas in a plasma coupler. The exhaust plasma is analyzed to determine an endpoint of the surface treatment. A system includes a process chamber configured to receive a wafer and perform a surface treatment on the wafer without plasma. The process chamber includes an outlet configured to output an exhaust gas of the surface treatment. A plasma coupler is configured to receive the exhaust gas and generate an exhaust plasma therefrom. A detector is configured to receive and analyze the exhaust plasma.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Applicant: Tokyo Electron Limited
    Inventors: Qi WANG, Steven GRZESKOWIAK, Nicholas SMIESZEK, Blaze MESSER, Sergey VORONIN, Akiteru KO, Eric Chih-Fang LIU, Ashawaraya SHALINI, Da SONG
  • Publication number: 20240096622
    Abstract: An embodiment etching tool includes an etch chamber for plasma etching a first wafer to be processed; a transfer chamber coupled to the etch chamber; a first run path between the transfer chamber and the etch chamber, the first run path including a path for moving the first wafer to be processed from the transfer chamber to the etch chamber, where the etching tool is configured to dry develop the first wafer to be processed before etching a hard mask on the first wafer in the etch chamber.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Inventors: Steven Grzeskowiak, Eric Chih-Fang Liu
  • Publication number: 20240087892
    Abstract: A method of forming a semiconductor device includes forming, over a hardmask layer and an underlying layer of a substrate, a pattern of first trenches between adjacent template lines, each of the first trenches exposing a portion of the hardmask layer, and each of the template lines including a mandrel and spacers on sidewalls of the mandrel; forming a pattern of first blocks over the pattern of the first trenches and the template lines, the first blocks dividing the first trenches to form a pattern of first stencil trenches; transferring the pattern of first stencil trenches to the hardmask layer to form a pattern of first hardmask trenches, each of the first hardmask trenches exposing a portion of the underlying layer; forming a first fill layer filling the first hardmask trenches and exposing the mandrels; selectively removing the mandrels to form second trenches, each of the second trenches exposing a portion of the hardmask layer; and forming a conformal liner in the second trenches and over a surface of
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Eric Chih-Fang Liu, Katie Lutker-Lee, Steven Grzeskowiak, Jodi Grzeskowiak, Jeffrey Smith, David L. O'Meara
  • Publication number: 20240063019
    Abstract: A method of forming a semiconductor device, where the method includes receiving a substrate in a processing chamber, the substrate including a first patterned layer including a metal-based material; and with a gaseous etch process, trimming the first patterned layer to form a second patterned layer, the gaseous etch process including exposing the first patterned layer to an un-ionized gas including a halogen compound.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Inventors: Alexandra Krawicz, Steven Grzeskowiak, Eric Chih-Fang Liu
  • Publication number: 20240047210
    Abstract: A method of processing a substrate that includes: forming recesses in a first mask layer over a mask stack including a lower hardmask, a middle mask, and an upper hardmask, the recesses defining an initial pattern including a plurality of spacer structures, each of the spacer structures having a first sidewall and an opposite second sidewall, the first sidewall having a different height from the second sidewall; etching the upper hardmask, selectively to the middle mask, to transfer the initial pattern to the upper hardmask; etching the middle mask, selectively to the lower hardmask and the patterned upper hardmask, to transfer a pattern of the patterned upper hardmask to the middle mask; and etching the lower hardmask, selectively to the patterned middle mask, to transfer a pattern of the patterned middle mask to the lower hardmask.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Inventors: Eric Chih-Fang Liu, Christopher Cole, Steven Grzeskowiak, Katie Lutker-Lee, Xinghua Sun, Daniel Santos Rivera
  • Publication number: 20230152705
    Abstract: A method includes loading a substrate with a resist including a pattern exposed with a first dose of UV light in the extreme ultraviolet (EUV) radiation region of the UV spectrum onto a developer track; blanket exposing the substrate with a second dose of ultraviolet light radiation in a first UV exposure module; and after the blanket exposing, developing the pattern.
    Type: Application
    Filed: November 17, 2021
    Publication date: May 18, 2023
    Inventors: Steven Grzeskowiak, Angelique Raley
  • Publication number: 20230078946
    Abstract: A method of microfabrication includes depositing a photoresist film on a working surface of a semiconductor wafer, the photoresist film being sensitive to extreme ultraviolet radiation; exposing the photoresist film to a pattern of extreme ultraviolet radiation; performing a hybrid develop of the photoresist film. The hybrid develop includes executing a first development process to remove a first portion of the photoresist film; stopping the development of the photoresist film after the first development process, the photo resist film including a structure having a first critical dimension larger than a target critical dimension after the stopping; and after stopping the development, executing a second development process to remove a second portion of the photoresist film and shrinking the critical dimension of the structure from the first critical dimension to a second critical dimension that is less than the first critical dimension.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 16, 2023
    Inventors: Steven Grzeskowiak, Lior Huli, Angelique Raley, Cong Que Dinh, Makoto Muramatsu, Seiji Nagahara