Abstract: Aspects of the disclosure provide a method for configuring a Quantum Annealing (QA) device. Then QA device has a plurality of qubits and a plurality of couplers at overlapping intersections of the qubits. The method includes mapping a node of a neural network that have a plurality of nodes and connections between the nodes to a qubit in the QA device, and mapping a connection of the neural network to a coupler at an intersection in the QA device where two qubits corresponding to two nodes connected by the connection intersect. The method further includes mapping a node of the neural network to a chain of qubits. In an embodiment, a coupling between qubits in the chain is configured to be a ferromagnetic coupling in order to map the node of the neural network to the chain of qubits.

Abstract: Methods are provided for implementing schemes for embedding a particular optimization problem into a particular hardware solution employing unique graph embedding techniques. The disclosed methods implement an adiabatic quantum optimization in a quantum computing device or a quantum processor. Heuristics for graph minor embedding are employed to map a problem graph structure of a particular binary unconstrained optimization problem onto a physical graph structure (topology) of the quantum computing device or quantum processor to provide an optimized hardware implementation. Known constraints that are presented with current schemes in their application to particular hardware solutions are avoided, including limited qubit connectivity and the presence of faulty qubits.

Abstract: Methods are provided for implementing schemes for embedding a particular optimization problem into a particular hardware solution employing unique graph embedding techniques. The disclosed methods implement an adiabatic quantum optimization in a quantum computing device or a quantum processor. Heuristics for graph minor embedding are employed to map a problem graph structure of a particular binary unconstrained optimization problem onto a physical graph structure (topology) of the quantum computing device or quantum processor to provide an optimized hardware implementation. Known constraints that are presented with current schemes in their application to particular hardware solutions are avoided, including limited qubit connectivity and the presence of faulty qubits.

Abstract: Aspects of the disclosure provide a method for configuring a Quantum Annealing (QA) device. Then QA device has a plurality of qubits and a plurality of couplers at overlapping intersections of the qubits. The method includes mapping a node of a neural network that have a plurality of nodes and connections between the nodes to a qubit in the QA device, and mapping a connection of the neural network to a coupler at an intersection in the QA device where two qubits corresponding to two nodes connected by the connection intersect. The method further includes mapping a node of the neural network to a chain of qubits. In an embodiment, a coupling between qubits in the chain is configured to be a ferromagnetic coupling in order to map the node of the neural network to the chain of qubits.