Patents by Inventor Steven H. Boettcher

Steven H. Boettcher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7560692
    Abstract: A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. The TEOS oxide marker is readily visible during the polish, has a similar polish rate as a semiconductor material, and reduces contamination during sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: July 14, 2009
    Assignees: International Business Machines Corporation, Dongbu Electronics Co., Ltd.
    Inventors: Keith E. Barton, Steven H. Boettcher, John G. Gaudiello, Leon J. Kimball, Yun-Yu Wang
  • Publication number: 20080237053
    Abstract: An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; wherein the opening has an underlayer of cobalt and/or nickel therein, barrier layer of an alloy of cobalt and/or nickel; and tungsten is provided.
    Type: Application
    Filed: May 27, 2008
    Publication date: October 2, 2008
    Applicant: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Steven H. Boettcher, Sandra G. Malhotra, Milan Paunovic, Craig Ransom
  • Publication number: 20080156987
    Abstract: A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. TEOS oxide marker is readily visible during the polish, has a similar polish rate as semiconductor material, and reduces contamination during the sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Barton, Steven H. Boettcher, John G. Gaudiello, Leon J. Kimball, Yun Yu Wang
  • Patent number: 7227265
    Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 ?m and via openings filled with electroplated copper than is substantially free of internal seams or voids.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: June 5, 2007
    Assignee: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, Steven H. Boettcher, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Christopher C. Parks, Soon-Cheon Seo, Andrew H. Simon, Erick G. Walton
  • Patent number: 7214935
    Abstract: A method for preparing a transmission electron microscopy (TEM) sample for electron holography includes forming a sacrificial material over an area of interest on the sample, and polishing the sample to a desired thickness, wherein the area of interest is protected from rounding during the polishing. The sacrificial material is removed from the sample following the polishing.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: May 8, 2007
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Bauer, Steven H. Boettcher, Anthony G. Domenicucci, John G. Gaudiello, Leon J. Kimball, Jeffrey S. McMurray, Yun-Yu Wang
  • Patent number: 6911229
    Abstract: An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; a barrier layer located in the via opening; an interlayer of palladium and/or platinum on the barrier layer; and a layer of copper or copper alloy on the interlayer is provided.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: June 28, 2005
    Assignee: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, Steven H. Boettcher, Fenton Read McFeely, Milan Paunovic
  • Publication number: 20040178078
    Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &mgr;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 16, 2004
    Applicant: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, Steven H. Boettcher, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Christopher C. Parks, Soon-Cheon Seo, Andrew H. Simon, Erick G. Walton
  • Publication number: 20040178077
    Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &mgr;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 16, 2004
    Applicant: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, Steven H. Boettcher, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Christopher C. Parks, Soon-Cheon Seo, Andrew H. Simon, Erick G. Walton
  • Publication number: 20040108136
    Abstract: An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; wherein the opening has an underlayer of cobalt and/or nickel therein, barrier layer of an alloy of cobalt and/or nickel; and tungsten is provided.
    Type: Application
    Filed: December 4, 2002
    Publication date: June 10, 2004
    Applicant: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Steven H. Boettcher, Sandra G. Malhotra, Milan Paunovic, Craig Ransom
  • Publication number: 20040028882
    Abstract: An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; a barrier layer located in the via opening; an interlayer of palladium and/or platinum on the barrier layer; and a layer of copper or copper alloy on the interlayer is provided.
    Type: Application
    Filed: August 9, 2002
    Publication date: February 12, 2004
    Inventors: Panayotis C. Andricacos, Steven H. Boettcher, Fenton Read McFeely, Milan Paunovic
  • Patent number: 6572982
    Abstract: An electromigration-resistant copper film structure and the process for forming the structure. The film structure contains a high impurity content, is resistant to grain growth, and possesses superior metallurgical, thermo-mechanical, and electrical properties. The process comprises the steps of: (a) providing a seed layer at least indirectly on a substrate, the seed layer having an exposed surface; (b) immersing the substrate in a plating solution; (c) electrodepositing a copper-containing film on the exposed surface of the seed layer, the copper-containing film having a first surface; (d) maintaining the substrate in an immersed state within the plating solution; (e) electrodepositing a further copper-containing film from the plating solution onto the first surface; (f) removing the substrate from the plating solution; and (g) drying the substrate.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: June 3, 2003
    Assignee: International Business Machines Corporation
    Inventors: Cyprian E. Uzoh, Steven H. Boettcher, Patrick W. DeHaven, Christopher C. Parks, Andrew H. Simon
  • Publication number: 20020092673
    Abstract: An interconnection structure is provided wherein comprises a substrate having a dielectric layer with a via opening therein; wherein the opening has a barrier layer; and electrodeposited copper.
    Type: Application
    Filed: January 17, 2001
    Publication date: July 18, 2002
    Applicant: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, Steven H. Boettcher, Fenton Read McFeely, Milan Paunovic
  • Patent number: 6416812
    Abstract: Copper is deposited onto a barrier layer such as tungsten from an electroless copper plating bath having a pH of at least 12.89 and a deposition rate of 50 nanometers/minute or less.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: July 9, 2002
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Steven H. Boettcher, Fenton Read McFeely, Milan Paunovic
  • Publication number: 20020081842
    Abstract: A semiconductor structure, having a semiconductor dielectric material having an opening. A first material lining the opening, the first material comprising MXY, where M is selected from the group consisting of cobalt and nickel, X is selected from the group consisting of tungsten and silicon and Y is selected from the group consisting of phosphorus and boron and a second material filling the lined dielectric material.
    Type: Application
    Filed: April 14, 2000
    Publication date: June 27, 2002
    Inventors: Carlos J. Sambucetti, Steven H. Boettcher, Peter S. Locke, Judith M. Rubino, Soon-Cheon Seo
  • Patent number: 6383929
    Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: May 7, 2002
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Steven H. Boettcher, Herbert L. Ho, Mark Hoinkis, Hyun Koo Lee, Yun-Yu Wang, Kwong Hon Wong
  • Patent number: 6123825
    Abstract: An electromigration-resistant copper film structure and the process for forming the structure. The film structure contains a high impurity content, is resistant to grain growth, and possesses superior metallurgical, thermo-mechanical, and electrical properties. The process comprises the steps of: (a) providing a seed layer at least indirectly on a substrate, the seed layer having an exposed surface; (b) immersing the substrate in a plating solution; (c) electrodepositing a copper-containing film on the exposed surface of the seed layer, the copper-containing film having a first surface; (d) maintaining the substrate in an immersed state within the plating solution; (e) electrodepositing a further copper-containing film from the plating solution onto the first surface; (f) removing the substrate from the plating solution; and (g) drying the substrate.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: September 26, 2000
    Assignee: International Business Machines Corporation
    Inventors: Cyprian E. Uzoh, Steven H. Boettcher, Patrick W. DeHaven, Christopher C. Parks, Andrew H. Simon