Abstract: The present invention is a system 10 for charging a plurality of remote computers that includes a plurality of switch members 12, each switch member 12 being connected to a predetermined quantity of remote computers via power lines 21 such that each switch member 12 has substantially the same quantity of remote computers connected thereto, a charge bank select member 13 for sequentially connecting each of the switch members 12 to a battery charger 18 such that the battery charger 18 simultaneously charges all remote computers connected to the switch member 12 that is connected to the battery charger 18, and a timer 20 that sets the time period that each switch member 12 is connected to the battery charger 18.

Abstract: A rectangular to phase converter (201) includes a first converter circuit (201B) which limits signals to a predetermined level. A phase selector (259) selects a relative phase from the limited signals. According to one aspect of the invention, input rectangular coordinate signals are mapped to the first quadrant in a first quadrant mapping circuit (201A) before the first quadrant signals are limited and the relative phase signal is returned to the original quadrant by an original quadrant mapping circuit (260).

Abstract: In a communications device, two coherent detection algorithms (102 and 103), one of which has a decision feedback equalizer (103), and a detector selection algorithm (104) are used to dynamically select a detector depending on whether delay spread distortion is present. First the correlation of the detector without the equalizer (102) is measured. If this correlation is greater than a predetermined threshold, the data from that detector (102) is used by the communications device. If the correlation is less than the threshold, the correlation of the detector with the equalizer (103) is measured. If this is less than the correlation of the detector without the equalizer (102), the data from the detector without the equalizer (102) is used, otherwise the data is taken from the equalizer (103). In any case, if the detector without the equalizer is used, the detector with the equalizer is turned off.

Abstract: In a receiver an apparatus and method substantially reduces time dispersion and multipath distortion in a received signal. An equalizer (109), including taps having gain coefficients, produces an equalized signal (110) responsive to the received signal (107) and an adaptive process signal (137), wherein the gain coefficients are adjusted responsive to the adaptive process signal (137). A first mixer (111) mixes the equalized signal (110) and a reference carrier signal (115) to produce a recovered modulated signal (119). A detector (112) detects an estimate signal (129) responsive to the recovered modulated signal (119). An error signal generator (139) generates an error signal (141) responsive to a difference between the recovered modulated signal (119) and the estimate signal (129). A second mixer (147) mixes the error signal (141) and the reference carrier signal (115) to produce the adaptive process signal (137).

Abstract: In a communications device, two coherent detection algorithms (102 and 103), one of which has a decision feedback equalizer (103), and a detector selection algorithm (104) are used to dynamically select a detector depending on whether delay spread distortion is present. First the correlation of the detector without the equalizer (102) is measured. If this correlation is greater than a predetermined threshold, the data from that detector (102) is used by the communications device. If the correlation is less than the threshold, the correlation of the detector with the equalizer (103) is measured. If this is less than the correlation of the detector without the equalizer (102), the data from the detector without the equalizer (102) is used, otherwise the data is taken from the equalizer (103).

Abstract: An improved method and apparatus for demodulators for MSK signals. Demodulation of the MSK signals is performed at base-band other than at IF frequencies. A digital signal processor is preferably used.

Abstract: The .pi./4-QPSK coherent detector of the present invention has a vector input and an output comprising recovered data in bit pair form. The .pi./4-QPSK coherent detector recovers bursts of data, in a TDMA system, that has been encoded in an amplitude modulated vector's phase angle. The .pi./4-QPSK coherent detector detects the .pi./4-QPSK constellation of the incoming modulated signal and outputs the recovered data stream.

Abstract: The .pi./4-QPSK coherent detector of the present invention has a vector input and an output comprising recovered data in bit pair form. The .pi./4-QPSK coherent detector recovers data that has been encoded in an amplitude modulated vector's phase angle. The .pi./4-QPSK coherent detector detects the .pi./4-QPSK constellation of the incoming modulated signal and outputs the recovered data stream.

Abstract: An improved bias control circuit (FIG. 2) is disclosed for a radio receiver (122) used in a communication system wherein a signalling preamble is sent prior to sending other information. The bias circuit (140) rapidly determines the DC voltage level representing the average frequency of the received signalling preamble (215), develops a DC bias voltage (275) proportional to the error in frequency between the receiver and the transmitted signal, and then selectively applies this bias voltage to the series coupling capacitor (240) located between the receiver detector (121) and the receiver processing circuitry (123). The circuit is adapted for a 0.2 GMSK receiver in a TDMA communication system, where a known 1100 bit synchronization preamble is sent in each user's TDM time slot.

Abstract: A clock recovery circuit for a digital TDM mobile radio transceiver is disclosed. In the "acquisition mode", a first phase-locked loop is configured to acquire synchronization with the input data signal, and a second phase-locked loop is coupled to the first PLL's output signal, thereby providing the recovered clock signal. The controller monitors the transmit control line and the received signal strength so as to switch the clock recovery circuit into a second configuration during a TDM transmit burst or a received signal fade. In this "hold mode", the second PLL is configured to free-run within a specified tolerance, while the first PLL is coupled to the second PLL's output signal. The controller maintains this "hold" configuration until the received signal is again present, and until the first PLL again acquires synchronization to the input data signal.

Abstract: A clock recovery device suitable for implementation in a DSP functions to correct a signal that includes the clock information for carrier frequency offsets, prior to extraction of the clock signal.

Abstract: A time division multiplexed (TDM) communication device controller is disclosed, which controls all signalling, synchronization and supervisory functions. In one embodiment, the invention operates to control a remote communication device having a vo-coder and buffering means. The remote communication device is enabled to operate as a dispatch, full duplex or a combination dispatch/full duplex communication device. In another embodiment, a primary station (repeater) is controlled to operate as a single frequency repeater (SFR) or as a multi-frequency TDM repeater.

Abstract: An automatic deviation control circuit for an angle modulated data transmitter is disclosed wherein the deviation level of modulated data is controlled by a modulation cancelling deviation error detection feedback loop. After the modulation is cancelled from a sample of modulated carrier by a predetermined value of deviation, residual modulation is detected, sampled following a predetermined number of like-level data bits, and applied to the modulation path gain to increase or decrease the deviation such that the residual modulation is minimized.

Abstract: Improved method and apparatus in the form of coherent demodulators for MSK signal or other angle-modulated carrier signals of substantially constant amplitude and continuous phase are provided. The coherent demodulators include a frequency doubler, a first mixer for multiplying the frequency doubled signal with a half clock signal to produce a carrier term signal, a bandpass filter for filtering the carrier term signal and a divider coupled to the carrier bandpass filter to produce a coherent carrier signal. The half clock signal is generated by multiplying the frequency doubled signal with the filtered ouput signal of the carrier bandpass filter by a second mixer, and bandpass filtering the output signal of the second mixer to produce the half clock signal. The received binary data modulated signal and the generated coherent carrier signal are input to a quadrature detector for recovering the binary data.