Abstract: An improved driver interface circuit for interfacing between low voltage, low drive capability logic signals and large capacitive loads requiring high speed, high voltage logic signals. The improvement comprising the use of the logic input signal to power gate a high level buffer contained in the driver and thereby minimize the power consumption during inactive periods.

Abstract: A timing generator and verifier is provided in which a PROM stores the timing constants that are employed by the generator. An address counter, which is driven by a clock timer, cycles through an associated portion of the PROM to provide a sequence of output signals which represent timing for a particular mode. If a different mode is selected, the address counter selects a different sequence of output bits. During Normal mode the address counter operates on a cyclic basis driven by a fixed frequency free running master clock. In Verify mode the address counter is stepped by the Host computer. The outputs of the PROM are coupled through a buffer and logic section, where the outputs may be modified before being coupled to an adder which accumulates a checksum based on the outputs of all of the bits for a particular selected timing.

Abstract: Speech compaction/replay apparatus for real time monitoring speech and filtering out periods of relative slence from a recording of the speech. The recording also containing synchronization and time code information for ensuring that on replay and in terms of real time the audio output will essentially replicates the analog speech input. The apparatus and technique minimizing the amount of storage media required to store the speech.

Abstract: A timing generator and verifier is provided in which a PROM stores the timing constants that are employed by the generator. An address counter, which is driven by a clock timer, cycles through an associated portion of the PROM to provide a sequence of output signals which represent timing for a particular mode. If a different mode is selected, the address counter selects a different sequence of output bits. During Normal mode the address counter operates on a cyclic basis driven by a fixed frequency free running master clock. In Verify mode the address counter is stepped by the Host computer. The outputs of the PROM are coupled through a buffer and logic section, where the outputs may be modified before being coupled to an adder which accumulates a checksum based on the outputs of all of the bits for a particular selected timing.